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asahi: Flush USC caches on the first draw

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It seems that when batches are submitted back to back, the USC can
retain cache contents between them. This causes a problem when the CPU
updates a VBO between batches, since some of those updates might not be
visible to the USC.

Looks like the VDM barrier command with one magic bit set fixes this, so
let's try that.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21538>
This commit is contained in:
Asahi Lina 2023-02-22 20:16:01 +09:00 • committed by Marge Bot
parent 70169c7488
commit 494cb2e5ca
1 changed files with 10 additions and 2 deletions
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12
src/gallium/drivers/asahi/agx_state.c
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@ -2488,8 +2488,6 @@ agx_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info,
batch->resolve |= ctx->zs->store;
}
batch->any_draws = true;
if (agx_update_vs(ctx))
ctx->dirty |= AGX_DIRTY_VS | AGX_DIRTY_VS_PROG;
else if (ctx->stage[PIPE_SHADER_VERTEX].dirty)
@ -2515,6 +2513,7 @@ agx_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info,
AGX_VDM_STATE_VERTEX_SHADER_WORD_1_LENGTH +
AGX_VDM_STATE_VERTEX_OUTPUTS_LENGTH +
AGX_VDM_STATE_VERTEX_UNKNOWN_LENGTH + 4 /* padding */ +
((!batch->any_draws) ? AGX_VDM_BARRIER_LENGTH : 0) +
AGX_INDEX_LIST_LENGTH + AGX_INDEX_LIST_BUFFER_LO_LENGTH +
AGX_INDEX_LIST_COUNT_LENGTH + AGX_INDEX_LIST_INSTANCES_LENGTH +
AGX_INDEX_LIST_START_LENGTH + AGX_INDEX_LIST_BUFFER_SIZE_LENGTH);
@ -2552,6 +2551,15 @@ agx_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info,
out += AGX_VDM_STATE_RESTART_INDEX_LENGTH;
}
if (!batch->any_draws) {
agx_pack(out, VDM_BARRIER, cfg) {
cfg.usc_cache_inval = true;
}
out += AGX_VDM_BARRIER_LENGTH;
}
batch->any_draws = true;
agx_pack(out, INDEX_LIST, cfg) {
cfg.primitive = prim;
cfg.instance_count_present = true;