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i965/fs: Use the correct base_mrf for spilling pairs in SIMD8

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Before, we were hard-coding the base_mrf based on dispatch width not number
of registers spilled at a time.  This caused us to emit instructions with a
base_mrf or 14 and a mlen of 3 so we used the magical non-existant m16
register.  This fixes the problem.

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Jason Ekstrand 2014-10-02 16:04:57 -07:00
parent 50d0e2e118
commit 493bfa54a5
1 changed files with 4 additions and 3 deletions
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7
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
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@ -656,11 +656,12 @@ void
fs_visitor::emit_spill(bblock_t *block, fs_inst *inst, fs_reg src,
uint32_t spill_offset, int count)
{
int spill_base_mrf = dispatch_width > 8 ? 13 : 14;
int reg_size = 1;
if (count % 2 == 0)
int spill_base_mrf = 14;
if (count % 2 == 0) {
spill_base_mrf = 13;
reg_size = 2;
}
for (int i = 0; i < count / reg_size; i++) {
fs_inst *spill_inst =