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ir3/cp: disable cat3 hw bug workaround on a6xx+

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This hw bug seems to be fixed on a6xx and later.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36324>
This commit is contained in:
Job Noorman 2025-07-23 17:16:56 +02:00 • committed by Marge Bot
parent 5f843f6dd6
commit 493a5679e2
3 changed files with 5 additions and 1 deletions
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1
src/freedreno/ir3/ir3_compiler.c
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@ -330,6 +330,7 @@ ir3_compiler_create(struct fd_device *dev, const struct fd_dev_id *dev_id,
compiler->bool_type = (compiler->gen >= 5) ? TYPE_U16 : TYPE_U32;
compiler->has_shared_regfile = compiler->gen >= 5;
compiler->has_bitwise_triops = compiler->gen >= 5;
compiler->cat3_rel_offset_0_quirk = compiler->gen <= 5;
/* The driver can't request this unless preambles are supported. */
if (options->push_ubo_with_preamble)

2
src/freedreno/ir3/ir3_compiler.h
View file

@ -304,6 +304,8 @@ struct ir3_compiler {
bool reading_shading_rate_requires_smask_quirk;
bool cat3_rel_offset_0_quirk;
struct {
/* The number of cycles needed for the result of one ALU operation to be
* available to another ALU operation. Only valid when the halfness of the

3
src/freedreno/ir3/ir3_cp.c
View file

@ -381,7 +381,8 @@ reg_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr,
* just somehow don't work out. This restriction may only
* apply if the first src is also CONST.
*/
if ((opc_cat(instr->opc) == 3) && (n == 2) &&
if (ctx->so->compiler->cat3_rel_offset_0_quirk &&
(opc_cat(instr->opc) == 3) && (n == 2) &&
(src_reg->flags & IR3_REG_RELATIV) && (src_reg->array.offset == 0))
return false;