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ac/gpu_info: add gfx12_supports_display_dcc

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33212>
This commit is contained in:
Samuel Pitoiset 2025-01-24 08:51:31 -08:00 • committed by Marge Bot
parent dea4b46f21
commit 48d199f3dc
4 changed files with 10 additions and 8 deletions
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5
src/amd/common/ac_gpu_info.c
View file

@ -1423,6 +1423,11 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
}
}
/* The kernel code translating tiling flags into a modifier was wrong
* until .58.
*/
info->gfx12_supports_display_dcc = info->gfx_level >= GFX12 && info->drm_minor >= 58;
info->has_stable_pstate = info->drm_minor >= 45;
if (info->gfx_level >= GFX12) {

1
src/amd/common/ac_gpu_info.h
View file

@ -157,6 +157,7 @@ struct radeon_info {
bool use_display_dcc_unaligned;
/* Allocate both aligned and unaligned DCC and use the retile blit. */
bool use_display_dcc_with_retile_blit;
bool gfx12_supports_display_dcc;
/* Memory info. */
uint32_t pte_fragment_size;

5
src/amd/common/ac_surface.c
View file

@ -3280,7 +3280,6 @@ static bool gfx12_compute_surface(struct ac_addrlib *addrlib, const struct radeo
surf->u.gfx9.uses_custom_pitch = true;
}
bool supports_display_dcc = info->drm_minor >= 58;
surf->u.gfx9.swizzle_mode = AddrSurfInfoIn.swizzleMode;
surf->u.gfx9.resource_type = (enum gfx9_resource_type)AddrSurfInfoIn.resourceType;
surf->u.gfx9.gfx12_enable_dcc = ac_modifier_has_dcc(surf->modifier) ||
@ -3289,7 +3288,7 @@ static bool gfx12_compute_surface(struct ac_addrlib *addrlib, const struct radeo
/* Always enable compression for Z/S and MSAA color by default. */
(surf->flags & RADEON_SURF_Z_OR_SBUFFER ||
config->info.samples > 1 ||
((supports_display_dcc || !(surf->flags & RADEON_SURF_SCANOUT)) &&
((info->gfx12_supports_display_dcc || !(surf->flags & RADEON_SURF_SCANOUT)) &&
/* This one is not strictly necessary. */
surf->u.gfx9.swizzle_mode != ADDR3_LINEAR)));
@ -3297,7 +3296,7 @@ static bool gfx12_compute_surface(struct ac_addrlib *addrlib, const struct radeo
surf->is_linear = surf->u.gfx9.swizzle_mode == ADDR3_LINEAR;
surf->is_displayable = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
surf->u.gfx9.resource_type != RADEON_RESOURCE_3D &&
(supports_display_dcc || !surf->u.gfx9.gfx12_enable_dcc);
(info->gfx12_supports_display_dcc || !surf->u.gfx9.gfx12_enable_dcc);
surf->thick_tiling = surf->u.gfx9.swizzle_mode >= ADDR3_4KB_3D;
if (surf->flags & RADEON_SURF_Z_OR_SBUFFER) {

7
src/gallium/drivers/radeonsi/si_texture.c
View file

@ -226,11 +226,8 @@ static int si_init_surface(struct si_screen *sscreen, struct radeon_surf *surfac
flags |= RADEON_SURF_NO_HTILE;
}
/* The kernel code translating tiling flags into a modifier was wrong
* until .58, so don't set these attributes for older versions.
*/
bool supports_display_dcc = sscreen->info.drm_minor >= 58;
if (!is_imported && (!(ptex->bind & PIPE_BIND_SCANOUT) || supports_display_dcc)) {
if (!is_imported && (!(ptex->bind & PIPE_BIND_SCANOUT) ||
sscreen->info.gfx12_supports_display_dcc)) {
enum pipe_format format = util_format_get_depth_only(ptex->format);
/* These should be set for both color and Z/S. */