mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
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freedreno/a6xx: Update SO registers for streams
These seem to be unchanged from a5xx, so a5xx could probably be updated too. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6962>
This commit is contained in:
Connor Abbott
Marge Bot
parent
92022f2846
commit
48cfaecd4f
8 changed files with 98 additions and 65 deletions
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@ -7239,7 +7239,7 @@ clusters:
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00000000 VPC_VAR[0x1].DISABLE: 0
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00000000 VPC_VAR[0x2].DISABLE: 0
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00000000 VPC_VAR[0x3].DISABLE: 0
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00000000 VPC_SO_CNTL: { 0 }
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00000000 VPC_SO_CNTL: { ADDR = 0 }
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00000000 VPC_SO_STREAM_COUNTS_LO: 0
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00000000 VPC_SO_STREAM_COUNTS_HI: 0
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00000000 VPC_SO[0].BUFFER_BASE: 0
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@ -7276,7 +7276,7 @@ clusters:
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00ff0001 VPC_GS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 }
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00ff0001 VPC_DS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 }
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ff00ff00 VPC_CNTL_0: { NUMNONPOSVAR = 0 | PRIMIDLOC = 255 | VIEWIDLOC = 255 }
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00000000 VPC_SO_BUF_CNTL: { 0 }
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00000000 VPC_SO_STREAM_CNTL: { BUF0_STREAM = 0 | BUF1_STREAM = 0 | BUF2_STREAM = 0 | BUF3_STREAM = 0 | STREAM_ENABLE = 0 }
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00000000 VPC_SO_DISABLE: { 0 }
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- context: 1
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00000000 VPC_VARYING_INTERP[0].MODE: 0
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@ -7301,7 +7301,7 @@ clusters:
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00000000 VPC_VAR[0x1].DISABLE: 0
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00000000 VPC_VAR[0x2].DISABLE: 0
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00000000 VPC_VAR[0x3].DISABLE: 0
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00000000 VPC_SO_CNTL: { 0 }
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00000000 VPC_SO_CNTL: { ADDR = 0 }
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00000000 VPC_SO_STREAM_COUNTS_LO: 0
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00000000 VPC_SO_STREAM_COUNTS_HI: 0
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00000000 VPC_SO[0].BUFFER_BASE: 0
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@ -7338,7 +7338,7 @@ clusters:
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00ff0001 VPC_GS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 }
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00ff0001 VPC_DS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 }
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ff00ff00 VPC_CNTL_0: { NUMNONPOSVAR = 0 | PRIMIDLOC = 255 | VIEWIDLOC = 255 }
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00000000 VPC_SO_BUF_CNTL: { 0 }
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00000000 VPC_SO_STREAM_CNTL: { BUF0_STREAM = 0 | BUF1_STREAM = 0 | BUF2_STREAM = 0 | BUF3_STREAM = 0 | STREAM_ENABLE = 0 }
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00000000 VPC_SO_DISABLE: { 0 }
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- cluster-name: CLUSTER_FE
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- context: 0
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@ -7347,7 +7347,7 @@ clusters:
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00ff0001 VPC_GS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 }
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00ff0001 VPC_DS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 }
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ff00ff00 VPC_CNTL_0: { NUMNONPOSVAR = 0 | PRIMIDLOC = 255 | VIEWIDLOC = 255 }
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00000000 VPC_SO_BUF_CNTL: { 0 }
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00000000 VPC_SO_STREAM_CNTL: { BUF0_STREAM = 0 | BUF1_STREAM = 0 | BUF2_STREAM = 0 | BUF3_STREAM = 0 | STREAM_ENABLE = 0 }
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00000000 VPC_SO_DISABLE: { 0 }
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00000000 PC_TESS_NUM_VERTEX: 0
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00000000 PC_HS_INPUT_SIZE: { SIZE = 0 }
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@ -7607,7 +7607,7 @@ clusters:
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00ff0001 VPC_GS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 }
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00ff0001 VPC_DS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 }
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ff00ff00 VPC_CNTL_0: { NUMNONPOSVAR = 0 | PRIMIDLOC = 255 | VIEWIDLOC = 255 }
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00000000 VPC_SO_BUF_CNTL: { 0 }
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00000000 VPC_SO_STREAM_CNTL: { BUF0_STREAM = 0 | BUF1_STREAM = 0 | BUF2_STREAM = 0 | BUF3_STREAM = 0 | STREAM_ENABLE = 0 }
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00000000 VPC_SO_DISABLE: { 0 }
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00000000 PC_TESS_NUM_VERTEX: 0
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00000000 PC_HS_INPUT_SIZE: { SIZE = 0 }
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@ -7870,16 +7870,16 @@ clusters:
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0000ffff VPC_VS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 }
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0000ffff VPC_GS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 }
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0000ffff VPC_DS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 }
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00000000 VPC_UNKNOWN_9107: 0
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00000000 VPC_UNKNOWN_9107: { 0 }
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00000003 VPC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES }
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00000000 VPC_UNKNOWN_9300: 0
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00ff0001 VPC_VS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 }
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00ff0001 VPC_GS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 }
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00ff0001 VPC_DS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 }
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ff00ff00 VPC_CNTL_0: { NUMNONPOSVAR = 0 | PRIMIDLOC = 255 | VIEWIDLOC = 255 }
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00000000 VPC_SO_BUF_CNTL: { 0 }
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00000000 VPC_SO_STREAM_CNTL: { BUF0_STREAM = 0 | BUF1_STREAM = 0 | BUF2_STREAM = 0 | BUF3_STREAM = 0 | STREAM_ENABLE = 0 }
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00000000 VPC_SO_DISABLE: { 0 }
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00000000 PC_UNKNOWN_9980: 0
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00000000 PC_RASTER_CNTL: { STREAM = 0 }
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00000003 PC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES }
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00000002 PC_PRIMITIVE_CNTL_0: { PROVOKING_VTX_LAST }
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00000001 PC_VS_OUT_CNTL: { STRIDE_IN_VPC = 1 | CLIP_MASK = 0 }
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@ -7897,16 +7897,16 @@ clusters:
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0000ffff VPC_VS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 }
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0000ffff VPC_GS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 }
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0000ffff VPC_DS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 }
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00000000 VPC_UNKNOWN_9107: 0
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00000000 VPC_UNKNOWN_9107: { 0 }
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00000003 VPC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES }
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00000000 VPC_UNKNOWN_9300: 0
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00ff0001 VPC_VS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 }
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00ff0001 VPC_GS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 }
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00ff0001 VPC_DS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 }
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ff00ff00 VPC_CNTL_0: { NUMNONPOSVAR = 0 | PRIMIDLOC = 255 | VIEWIDLOC = 255 }
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00000000 VPC_SO_BUF_CNTL: { 0 }
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00000000 VPC_SO_STREAM_CNTL: { BUF0_STREAM = 0 | BUF1_STREAM = 0 | BUF2_STREAM = 0 | BUF3_STREAM = 0 | STREAM_ENABLE = 0 }
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00000000 VPC_SO_DISABLE: { 0 }
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00000000 PC_UNKNOWN_9980: 0
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00000000 PC_RASTER_CNTL: { STREAM = 0 }
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00000003 PC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES }
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00000002 PC_PRIMITIVE_CNTL_0: { PROVOKING_VTX_LAST }
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00000001 PC_VS_OUT_CNTL: { STRIDE_IN_VPC = 1 | CLIP_MASK = 0 }
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@ -127,7 +127,7 @@ t4 write RB_UNKNOWN_88F0 (88f0)
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RB_UNKNOWN_88F0: 0
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000000000105813c: 0000: 4888f001 00000000
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t4 write VPC_UNKNOWN_9107 (9107)
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VPC_UNKNOWN_9107: 0
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VPC_UNKNOWN_9107: { 0 }
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0000000001058144: 0000: 48910701 00000000
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t4 write VPC_POINT_COORD_INVERT (9236)
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VPC_POINT_COORD_INVERT: { 0 }
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@ -138,8 +138,8 @@ t4 write VPC_UNKNOWN_9300 (9300)
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t4 write VPC_SO_DISABLE (9306)
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VPC_SO_DISABLE: { DISABLE }
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000000000105815c: 0000: 48930601 00000001
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t4 write PC_UNKNOWN_9980 (9980)
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PC_UNKNOWN_9980: 0
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t4 write PC_RASTER_CNTL (9980)
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PC_RASTER_CNTL: { STREAM = 0 }
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0000000001058164: 0000: 40998001 00000000
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t4 write PC_PRIMITIVE_CNTL_6 (9b06)
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PC_PRIMITIVE_CNTL_6: { STRIDE_IN_VPC = 0 }
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@ -324,7 +324,7 @@ t7 opcode: CP_BLIT (2c) (2 dwords)
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+ 00000000 RB_UNKNOWN_8E01: 0
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!+ 00100000 RB_UNKNOWN_8E04: 0x100000
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!+ 10000000 RB_CCU_CNTL: { OFFSET = 0x20000 }
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+ 00000000 VPC_UNKNOWN_9107: 0
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+ 00000000 VPC_UNKNOWN_9107: { 0 }
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+ 00000000 VPC_UNKNOWN_9210: 0
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+ 00000000 VPC_UNKNOWN_9211: 0
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+ 00000000 VPC_POINT_COORD_INVERT: { 0 }
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@ -333,7 +333,7 @@ t7 opcode: CP_BLIT (2c) (2 dwords)
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+ 00000000 VPC_UNKNOWN_9600: 0
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+ 00000000 VPC_UNKNOWN_9602: FALSE
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!+ 0000001f PC_MODE_CNTL: 0x1f
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+ 00000000 PC_UNKNOWN_9980: 0
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+ 00000000 PC_RASTER_CNTL: { STREAM = 0 }
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+ 00000000 PC_PRIMITIVE_CNTL_6: { STRIDE_IN_VPC = 0 }
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+ 00000000 PC_MULTIVIEW_CNTL: { VIEWS = 0 }
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+ 00000000 PC_UNKNOWN_9E72: 0
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@ -966,8 +966,8 @@ t4 write VPC_VAR[0].DISABLE (9212)
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VPC_VAR[0x3].DISABLE: 0xffffffff
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000000000105427c: 0000: 40921204 fffffff0 ffffffff ffffffff ffffffff
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t7 opcode: CP_CONTEXT_REG_BUNCH (5c) (5 dwords)
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VPC_SO_CNTL: { 0 }
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VPC_SO_BUF_CNTL: { 0 }
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VPC_SO_CNTL: { ADDR = 0 }
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VPC_SO_STREAM_CNTL: { BUF0_STREAM = 0 | BUF1_STREAM = 0 | BUF2_STREAM = 0 | BUF3_STREAM = 0 | STREAM_ENABLE = 0 }
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0000000001054290: 0000: 70dc0004 00009216 00000000 00009305 00000000
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t4 write SP_VS_OUT[0].REG (a803)
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SP_VS_OUT[0].REG: { A_REGID = r2.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0xf }
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@ -1446,10 +1446,10 @@ t7 opcode: CP_DRAW_INDIRECT_MULTI (2a) (12 dwords)
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!+ ffffffff VPC_VAR[0x1].DISABLE: 0xffffffff
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!+ ffffffff VPC_VAR[0x2].DISABLE: 0xffffffff
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!+ ffffffff VPC_VAR[0x3].DISABLE: 0xffffffff
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+ 00000000 VPC_SO_CNTL: { 0 }
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+ 00000000 VPC_SO_CNTL: { ADDR = 0 }
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!+ 00ff0408 VPC_VS_PACK: { STRIDE_IN_VPC = 8 | POSITIONLOC = 4 | PSIZELOC = 255 | EXTRAPOS = 0 }
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!+ ff01ff04 VPC_CNTL_0: { NUMNONPOSVAR = 4 | PRIMIDLOC = 255 | VARYING | VIEWIDLOC = 255 }
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+ 00000000 VPC_SO_BUF_CNTL: { 0 }
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+ 00000000 VPC_SO_STREAM_CNTL: { BUF0_STREAM = 0 | BUF1_STREAM = 0 | BUF2_STREAM = 0 | BUF3_STREAM = 0 | STREAM_ENABLE = 0 }
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!+ ffffffff PC_RESTART_INDEX: 4294967295
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+ 00000000 PC_PRIMID_PASSTHRU: FALSE
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!+ 00000003 PC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES }
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@ -129,8 +129,8 @@ t4 write PC_PRIMID_PASSTHRU (9806)
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t4 write 0x9990 (9990)
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0x9990: 00000000
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0000000001d91144: 0000: 48999001 00000000
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t4 write PC_UNKNOWN_9980 (9980)
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PC_UNKNOWN_9980: 0
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t4 write PC_RASTER_CNTL (9980)
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PC_RASTER_CNTL: { STREAM = 0 }
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0000000001d9114c: 0000: 40998001 00000000
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t4 write PC_MULTIVIEW_CNTL (9b07)
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PC_MULTIVIEW_CNTL: { VIEWS = 0 }
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@ -224,8 +224,8 @@ t7 opcode: CP_SET_DRAW_STATE (43) (4 dwords)
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{ ADDR_LO = 0 }
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{ ADDR_HI = 0 }
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0000000001d91238: 0000: 70438003 00040000 00000000 00000000
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t4 write VPC_SO_BUF_CNTL (9305)
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VPC_SO_BUF_CNTL: { 0 }
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t4 write VPC_SO_STREAM_CNTL (9305)
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VPC_SO_STREAM_CNTL: { BUF0_STREAM = 0 | BUF1_STREAM = 0 | BUF2_STREAM = 0 | BUF3_STREAM = 0 | STREAM_ENABLE = 0 }
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0000000001d91248: 0000: 48930501 00000000
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t4 write GRAS_LRZ_CNTL (8100)
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GRAS_LRZ_CNTL: { 0 }
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@ -755,7 +755,7 @@ t4 write VPC_VS_CLIP_CNTL (9101)
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VPC_VS_CLIP_CNTL: { CLIP_MASK = 0 | CLIP_DIST_03_LOC = 255 | CLIP_DIST_47_LOC = 255 }
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0000000001121140: 0000: 48910101 00ffff00
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t4 write VPC_UNKNOWN_9107 (9107)
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VPC_UNKNOWN_9107: 0
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VPC_UNKNOWN_9107: { 0 }
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0000000001121148: 0000: 48910701 00000000
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t4 write VFD_CONTROL_1 (a001)
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VFD_CONTROL_1: { REGID4VTX = r63.x | REGID4INST = r63.x | REGID4PRIMID = r63.x | REGID4VIEWID = r63.x }
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@ -1041,7 +1041,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
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!+ 7c400004 RB_CCU_CNTL: { OFFSET = 0xf8000 | GMEM | UNK2 }
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!+ 00ffff00 VPC_VS_CLIP_CNTL: { CLIP_MASK = 0 | CLIP_DIST_03_LOC = 255 | CLIP_DIST_47_LOC = 255 }
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!+ 0000ffff VPC_VS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 }
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+ 00000000 VPC_UNKNOWN_9107: 0
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+ 00000000 VPC_UNKNOWN_9107: { 0 }
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!+ 00000003 VPC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES }
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+ 00000000 VPC_UNKNOWN_9210: 0
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+ 00000000 VPC_UNKNOWN_9211: 0
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@ -1053,7 +1053,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
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+ 00000000 VPC_UNKNOWN_9300: 0
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!+ 00ff0004 VPC_VS_PACK: { STRIDE_IN_VPC = 4 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 }
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!+ ff00ff00 VPC_CNTL_0: { NUMNONPOSVAR = 0 | PRIMIDLOC = 255 | VIEWIDLOC = 255 }
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+ 00000000 VPC_SO_BUF_CNTL: { 0 }
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+ 00000000 VPC_SO_STREAM_CNTL: { BUF0_STREAM = 0 | BUF1_STREAM = 0 | BUF2_STREAM = 0 | BUF3_STREAM = 0 | STREAM_ENABLE = 0 }
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+ 00000000 VPC_SO_DISABLE: { 0 }
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+ 00000000 VPC_UNKNOWN_9600: 0
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+ 00000000 VPC_UNKNOWN_9602: FALSE
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@ -1061,7 +1061,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
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!+ 0000001f PC_MODE_CNTL: 0x1f
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!+ 00000001 PC_UNKNOWN_9805: 0x1
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+ 00000000 PC_PRIMID_PASSTHRU: FALSE
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+ 00000000 PC_UNKNOWN_9980: 0
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+ 00000000 PC_RASTER_CNTL: { STREAM = 0 }
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!+ 00000003 PC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES }
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+ 00000000 0x9990: 00000000
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!+ 00000002 PC_PRIMITIVE_CNTL_0: { PROVOKING_VTX_LAST }
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@ -2070,7 +2070,7 @@ t4 write VPC_VS_CLIP_CNTL (9101)
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VPC_VS_CLIP_CNTL: { CLIP_MASK = 0 | CLIP_DIST_03_LOC = 255 | CLIP_DIST_47_LOC = 255 }
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0000000001120140: 0000: 48910101 00ffff00
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t4 write VPC_UNKNOWN_9107 (9107)
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VPC_UNKNOWN_9107: 0
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VPC_UNKNOWN_9107: { 0 }
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0000000001120148: 0000: 48910701 00000000
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t4 write SP_FS_INSTRLEN (ab05)
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SP_FS_INSTRLEN: 88
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@ -5272,7 +5272,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
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+ 00000000 RB_STENCILWRMASK: { WRMASK = 0 | BFWRMASK = 0 }
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+ 00ffff00 VPC_VS_CLIP_CNTL: { CLIP_MASK = 0 | CLIP_DIST_03_LOC = 255 | CLIP_DIST_47_LOC = 255 }
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+ 0000ffff VPC_VS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 }
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+ 00000000 VPC_UNKNOWN_9107: 0
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+ 00000000 VPC_UNKNOWN_9107: { 0 }
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+ 00000000 VPC_VARYING_INTERP[0].MODE: 0
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+ 00000000 VPC_VARYING_INTERP[0x1].MODE: 0
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+ 00000000 VPC_VARYING_INTERP[0x2].MODE: 0
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@ -2670,7 +2670,11 @@ to upconvert to 32b float internally?
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<reg32 offset="0x9105" name="VPC_GS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl"/>
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<reg32 offset="0x9106" name="VPC_DS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl"/>
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<reg32 offset="0x9107" name="VPC_UNKNOWN_9107" pos="2"/>
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<reg32 offset="0x9107" name="VPC_UNKNOWN_9107">
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<!-- this mirrors PC_RASTER_CNTL::DISCARD, although it seems it's unused -->
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<bitfield name="RASTER_DISCARD" pos="0" type="boolean"/>
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<bitfield name="UNK2" pos="2" type="boolean"/>
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</reg32>
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<reg32 offset="0x9108" name="VPC_POLYGON_MODE">
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<bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
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</reg32>
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@ -2692,9 +2696,32 @@ to upconvert to 32b float internally?
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</array>
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<reg32 offset="0x9216" name="VPC_SO_CNTL">
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<bitfield name="UNK0" low="0" high="7"/>
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<!-- always 0x10000 when SO enabled.. -->
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<bitfield name="ENABLE" pos="16" type="boolean"/>
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<!--
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Choose which DWORD to write to. There is an array of
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(4 * 64) DWORD's, dumped in the devcoredump at
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HLSQ_INST_RAM dword 0x400. Each DWORD corresponds to a
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(VPC location, stream) pair like so:
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location 0, stream 0
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location 2, stream 0
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...
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location 126, stream 0
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location 0, stream 1
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location 2, stream 1
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...
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location 126, stream 1
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location 0, stream 2
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...
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When EmitStreamVertex(N) happens, the HW goes to DWORD
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64 * N and then "executes" the next 64 DWORD's.
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This field is auto-incremented when VPC_SO_PROG is
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written to.
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-->
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<bitfield name="ADDR" low="0" high="7" type="hex"/>
|
||||
<!-- clear all A_EN and B_EN bits for all DWORD's -->
|
||||
<bitfield name="RESET" pos="16" type="boolean"/>
|
||||
</reg32>
|
||||
<!-- special register, write multiple times to load SO program (not readable) -->
|
||||
<reg32 offset="0x9217" name="VPC_SO_PROG">
|
||||
|
|
@ -2769,14 +2796,15 @@ to upconvert to 32b float internally?
|
|||
</bitfield>
|
||||
</reg32>
|
||||
|
||||
<reg32 offset="0x9305" name="VPC_SO_BUF_CNTL">
|
||||
<!-- TODO: the first 12 bits are valid, likely 3-bit enum instead of bools -->
|
||||
<bitfield name="BUF0" pos="0" type="boolean"/>
|
||||
<bitfield name="BUF1" pos="3" type="boolean"/>
|
||||
<bitfield name="BUF2" pos="6" type="boolean"/>
|
||||
<bitfield name="BUF3" pos="9" type="boolean"/>
|
||||
<bitfield name="ENABLE" pos="15" type="boolean"/>
|
||||
<bitfield name="UNK16" low="16" high="19"/>
|
||||
<reg32 offset="0x9305" name="VPC_SO_STREAM_CNTL">
|
||||
<!--
|
||||
It's offset by 1, and 0 means "disabled"
|
||||
-->
|
||||
<bitfield name="BUF0_STREAM" low="0" high="2" type="uint"/>
|
||||
<bitfield name="BUF1_STREAM" low="3" high="5" type="uint"/>
|
||||
<bitfield name="BUF2_STREAM" low="6" high="8" type="uint"/>
|
||||
<bitfield name="BUF3_STREAM" low="9" high="11" type="uint"/>
|
||||
<bitfield name="STREAM_ENABLE" low="15" high="18" type="hex"/>
|
||||
</reg32>
|
||||
<reg32 offset="0x9306" name="VPC_SO_DISABLE">
|
||||
<bitfield name="DISABLE" pos="0" type="boolean"/>
|
||||
|
|
@ -2852,7 +2880,13 @@ to upconvert to 32b float internally?
|
|||
<reg32 offset="0x9981" name="PC_POLYGON_MODE">
|
||||
<bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
|
||||
</reg32>
|
||||
<reg32 offset="0x9980" name="PC_UNKNOWN_9980" low="0" high="2"/>
|
||||
|
||||
<reg32 offset="0x9980" name="PC_RASTER_CNTL">
|
||||
<!-- which stream to send to GRAS -->
|
||||
<bitfield name="STREAM" low="0" high="1" type="uint"/>
|
||||
<!-- discard primitives before rasterization -->
|
||||
<bitfield name="DISCARD" pos="2" type="boolean"/>
|
||||
</reg32>
|
||||
|
||||
<!-- 0x9982-0x9aff invalid -->
|
||||
|
||||
|
|
|
|||
|
|
@ -778,7 +778,7 @@ tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
|
|||
|
||||
tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(true));
|
||||
|
||||
tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9980, 0);
|
||||
tu_cs_emit_write_reg(cs, REG_A6XX_PC_RASTER_CNTL, 0);
|
||||
|
||||
tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A81B, 0);
|
||||
|
||||
|
|
|
|||
|
|
@ -619,7 +619,7 @@ tu6_setup_streamout(struct tu_cs *cs,
|
|||
tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 4);
|
||||
tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
|
||||
tu_cs_emit(cs, 0);
|
||||
tu_cs_emit(cs, REG_A6XX_VPC_SO_BUF_CNTL);
|
||||
tu_cs_emit(cs, REG_A6XX_VPC_SO_STREAM_CNTL);
|
||||
tu_cs_emit(cs, 0);
|
||||
return;
|
||||
}
|
||||
|
|
@ -664,19 +664,18 @@ tu6_setup_streamout(struct tu_cs *cs,
|
|||
}
|
||||
|
||||
tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 12 + 2 * prog_count);
|
||||
tu_cs_emit(cs, REG_A6XX_VPC_SO_BUF_CNTL);
|
||||
tu_cs_emit(cs, A6XX_VPC_SO_BUF_CNTL_ENABLE |
|
||||
COND(ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
|
||||
COND(ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
|
||||
COND(ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
|
||||
COND(ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3));
|
||||
tu_cs_emit(cs, REG_A6XX_VPC_SO_STREAM_CNTL);
|
||||
tu_cs_emit(cs, A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(0x1) |
|
||||
COND(ncomp[0] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(1)) |
|
||||
COND(ncomp[1] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(1)) |
|
||||
COND(ncomp[2] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(1)) |
|
||||
COND(ncomp[3] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(1)));
|
||||
for (uint32_t i = 0; i < 4; i++) {
|
||||
tu_cs_emit(cs, REG_A6XX_VPC_SO_NCOMP(i));
|
||||
tu_cs_emit(cs, ncomp[i]);
|
||||
}
|
||||
/* note: "VPC_SO_CNTL" write seems to be responsible for resetting the SO_PROG */
|
||||
tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
|
||||
tu_cs_emit(cs, A6XX_VPC_SO_CNTL_ENABLE);
|
||||
tu_cs_emit(cs, A6XX_VPC_SO_CNTL_RESET);
|
||||
for (uint32_t i = 0; i < prog_count; i++) {
|
||||
tu_cs_emit(cs, REG_A6XX_VPC_SO_PROG);
|
||||
tu_cs_emit(cs, prog[i]);
|
||||
|
|
|
|||
|
|
@ -772,7 +772,7 @@ fd6_emit_streamout(struct fd_ringbuffer *ring, struct fd6_emit *emit, struct ir3
|
|||
OUT_PKT7(obj, CP_CONTEXT_REG_BUNCH, 4);
|
||||
OUT_RING(obj, REG_A6XX_VPC_SO_CNTL);
|
||||
OUT_RING(obj, 0);
|
||||
OUT_RING(obj, REG_A6XX_VPC_SO_BUF_CNTL);
|
||||
OUT_RING(obj, REG_A6XX_VPC_SO_STREAM_CNTL);
|
||||
OUT_RING(obj, 0);
|
||||
|
||||
fd6_emit_take_group(emit, obj, FD6_GROUP_SO, ENABLE_ALL);
|
||||
|
|
@ -1211,7 +1211,7 @@ fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
|
|||
|
||||
WRITE(REG_A6XX_VPC_SO_DISABLE, A6XX_VPC_SO_DISABLE(true).value);
|
||||
|
||||
WRITE(REG_A6XX_PC_UNKNOWN_9980, 0);
|
||||
WRITE(REG_A6XX_PC_RASTER_CNTL, 0);
|
||||
|
||||
WRITE(REG_A6XX_PC_MULTIVIEW_CNTL, 0);
|
||||
|
||||
|
|
@ -1256,8 +1256,8 @@ fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
|
|||
OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
|
||||
OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
|
||||
|
||||
OUT_PKT4(ring, REG_A6XX_VPC_SO_BUF_CNTL, 1);
|
||||
OUT_RING(ring, 0x00000000); /* VPC_SO_BUF_CNTL */
|
||||
OUT_PKT4(ring, REG_A6XX_VPC_SO_STREAM_CNTL, 1);
|
||||
OUT_RING(ring, 0x00000000); /* VPC_SO_STREAM_CNTL */
|
||||
|
||||
OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
|
||||
OUT_RING(ring, 0x00000000);
|
||||
|
|
|
|||
|
|
@ -201,12 +201,12 @@ setup_stream_out(struct fd6_program_state *state, const struct ir3_shader_varian
|
|||
struct fd_ringbuffer *ring = state->streamout_stateobj;
|
||||
|
||||
OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, 12 + (2 * prog_count));
|
||||
OUT_RING(ring, REG_A6XX_VPC_SO_BUF_CNTL);
|
||||
OUT_RING(ring, A6XX_VPC_SO_BUF_CNTL_ENABLE |
|
||||
COND(ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
|
||||
COND(ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
|
||||
COND(ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
|
||||
COND(ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3));
|
||||
OUT_RING(ring, REG_A6XX_VPC_SO_STREAM_CNTL);
|
||||
OUT_RING(ring, A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(0x1) |
|
||||
COND(ncomp[0] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(1)) |
|
||||
COND(ncomp[1] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(1)) |
|
||||
COND(ncomp[2] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(1)) |
|
||||
COND(ncomp[3] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(1)));
|
||||
OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(0));
|
||||
OUT_RING(ring, ncomp[0]);
|
||||
OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(1));
|
||||
|
|
@ -216,7 +216,7 @@ setup_stream_out(struct fd6_program_state *state, const struct ir3_shader_varian
|
|||
OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(3));
|
||||
OUT_RING(ring, ncomp[3]);
|
||||
OUT_RING(ring, REG_A6XX_VPC_SO_CNTL);
|
||||
OUT_RING(ring, A6XX_VPC_SO_CNTL_ENABLE);
|
||||
OUT_RING(ring, A6XX_VPC_SO_CNTL_RESET);
|
||||
for (unsigned i = 0; i < prog_count; i++) {
|
||||
OUT_RING(ring, REG_A6XX_VPC_SO_PROG);
|
||||
OUT_RING(ring, prog[i]);
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue