diff --git a/src/amd/common/ac_cmdbuf.c b/src/amd/common/ac_cmdbuf.c index 257c573f76f..7d9fd31c637 100644 --- a/src/amd/common/ac_cmdbuf.c +++ b/src/amd/common/ac_cmdbuf.c @@ -1069,3 +1069,21 @@ ac_emit_cp_pfp_sync_me(struct ac_cmdbuf *cs) ac_cmdbuf_emit(0); ac_cmdbuf_end(); } + +void +ac_emit_cp_set_predication(struct ac_cmdbuf *cs, enum amd_gfx_level gfx_level, + uint64_t va, uint32_t op) +{ + ac_cmdbuf_begin(cs); + if (gfx_level >= GFX9) { + ac_cmdbuf_emit(PKT3(PKT3_SET_PREDICATION, 2, 0)); + ac_cmdbuf_emit(op); + ac_cmdbuf_emit(va); + ac_cmdbuf_emit(va >> 32); + } else { + ac_cmdbuf_emit(PKT3(PKT3_SET_PREDICATION, 1, 0)); + ac_cmdbuf_emit(va); + ac_cmdbuf_emit(op | ((va >> 32) & 0xFF)); + } + ac_cmdbuf_end(); +} diff --git a/src/amd/common/ac_cmdbuf.h b/src/amd/common/ac_cmdbuf.h index 09d3d64dc8f..ec722534ecb 100644 --- a/src/amd/common/ac_cmdbuf.h +++ b/src/amd/common/ac_cmdbuf.h @@ -134,6 +134,10 @@ ac_emit_cp_copy_data(struct ac_cmdbuf *cs, uint32_t src_sel, uint32_t dst_sel, void ac_emit_cp_pfp_sync_me(struct ac_cmdbuf *cs); +void +ac_emit_cp_set_predication(struct ac_cmdbuf *cs, enum amd_gfx_level gfx_level, + uint64_t va, uint32_t op); + #ifdef __cplusplus } #endif diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index b1bb8e4364a..64ec5e37a28 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -14605,25 +14605,14 @@ radv_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, bool draw_vi op = PRED_OP(pred_op); - /* PREDICATION_DRAW_VISIBLE means that if the 32-bit value is - * zero, all rendering commands are discarded. Otherwise, they - * are discarded if the value is non zero. + /* PREDICATION_DRAW_VISIBLE means that if the 32-bit value is zero, all + * rendering commands are discarded. Otherwise, they are discarded if + * the value is non zero. */ op |= draw_visible ? PREDICATION_DRAW_VISIBLE : PREDICATION_DRAW_NOT_VISIBLE; } - radeon_begin(cs); - if (pdev->info.gfx_level >= GFX9) { - radeon_emit(PKT3(PKT3_SET_PREDICATION, 2, 0)); - radeon_emit(op); - radeon_emit(va); - radeon_emit(va >> 32); - } else { - radeon_emit(PKT3(PKT3_SET_PREDICATION, 1, 0)); - radeon_emit(va); - radeon_emit(op | ((va >> 32) & 0xFF)); - } - radeon_end(); + ac_emit_cp_set_predication(cs->b, pdev->info.gfx_level, va, op); } void diff --git a/src/gallium/drivers/radeonsi/si_query.c b/src/gallium/drivers/radeonsi/si_query.c index 9047319fb31..b148412c81f 100644 --- a/src/gallium/drivers/radeonsi/si_query.c +++ b/src/gallium/drivers/radeonsi/si_query.c @@ -1033,19 +1033,7 @@ static void emit_set_predicate(struct si_context *ctx, struct si_resource *buf, { struct radeon_cmdbuf *cs = &ctx->gfx_cs; - radeon_begin(cs); - - if (ctx->gfx_level >= GFX9) { - radeon_emit(PKT3(PKT3_SET_PREDICATION, 2, 0)); - radeon_emit(op); - radeon_emit(va); - radeon_emit(va >> 32); - } else { - radeon_emit(PKT3(PKT3_SET_PREDICATION, 1, 0)); - radeon_emit(va); - radeon_emit(op | ((va >> 32) & 0xFF)); - } - radeon_end(); + ac_emit_cp_set_predication(&cs->current, ctx->gfx_level, va, op); radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, buf, RADEON_USAGE_READ | RADEON_PRIO_QUERY); }