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aco: use v1b/v2b for ds_read_u8/ds_read_u16

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The p_extract_vector isn't necessary.

For ds_read_u8 and ds_read_u16, we used a 32-bit regclass, but did't load
32 bits, and used dst_hint for vector loads when we shouldn't have.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4863
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11113>
This commit is contained in:
Rhys Perry 2021-05-31 18:18:24 +01:00 • committed by Marge Bot
parent 2fb436e92a
commit 4870d7d829
2 changed files with 6 additions and 4 deletions
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5
src/amd/compiler/aco_instruction_selection.cpp
View file

@ -3708,7 +3708,7 @@ Temp lds_load_callback(Builder& bld, const LoadEmitInfo &info,
const_offset /= const_offset_unit;
RegClass rc = RegClass(RegType::vgpr, DIV_ROUND_UP(size, 4));
RegClass rc = RegClass::get(RegType::vgpr, size);
Temp val = rc == info.dst.regClass() && dst_hint.id() ? dst_hint : bld.tmp(rc);
Instruction *instr;
if (read2)
@ -3717,9 +3717,6 @@ Temp lds_load_callback(Builder& bld, const LoadEmitInfo &info,
instr = bld.ds(op, Definition(val), offset, m, const_offset);
instr->ds().sync = info.sync;
if (size < 4)
val = bld.pseudo(aco_opcode::p_extract_vector, bld.def(RegClass::get(RegType::vgpr, size)), val, Operand(0u));
return val;
}

5
src/amd/compiler/aco_opcodes.py
View file

@ -1696,3 +1696,8 @@ for ver in ['gfx9', 'gfx10']:
sys.exit(1)
else:
op_to_name[key] = op.name
# These instructions write the entire 32-bit VGPR, but it's not clear in Opcode's constructor that
# it should be 32, since it works accidentally.
assert(opcodes['ds_read_u8'].definition_size == 32)
assert(opcodes['ds_read_u16'].definition_size == 32)