r300-gallium: Fix scissors.

Don't use SCISSORS_OFFSET since we're DRI2,
and don't forget to set scissors in clear.
This commit is contained in:
Corbin Simpson 2009-02-14 15:24:44 -08:00
parent 4e309b5d64
commit 484858ae48
5 changed files with 29 additions and 20 deletions

View file

@ -36,8 +36,8 @@
} while (0)
#define R300_PACIFY do { \
OUT_CS_REG(RADEON_WAIT_UNTIL, (1 << 15) | (1 << 17) | \
(1 << 18) | (1 << 31)); \
OUT_CS_REG(RADEON_WAIT_UNTIL, (1 << 14) | (1 << 15) | (1 << 16) | (1 << 17) | \
(1 << 18)); \
} while (0)
#define R300_SCREENDOOR do { \

View file

@ -208,6 +208,17 @@ void r300_emit_rs_state(struct r300_context* r300, struct r300_rs_state* rs)
END_CS;
}
void r300_emit_scissor_state(struct r300_context* r300,
struct r300_scissor_state* scissor)
{
CS_LOCALS(r300);
BEGIN_CS(3);
OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
OUT_CS(scissor->scissor_top_left);
OUT_CS(scissor->scissor_bottom_right);
}
/* Emit all dirty state. */
static void r300_emit_dirty_state(struct r300_context* r300)
{
struct r300_screen* r300screen =
@ -247,10 +258,7 @@ static void r300_emit_dirty_state(struct r300_context* r300)
}
if (r300->dirty_state & R300_NEW_SCISSOR) {
struct r300_scissor_state* scissor = r300->scissor_state;
/* XXX next two are contiguous regs */
OUT_CS_REG(R300_SC_SCISSORS_TL, scissor->scissor_top_left);
OUT_CS_REG(R300_SC_SCISSORS_BR, scissor->scissor_bottom_right);
r300_emit_scissor_state(r300, r300->scissor_state);
}
r300->dirty_state = 0;

View file

@ -45,3 +45,6 @@ void r300_emit_fb_state(struct r300_context* r300,
struct pipe_framebuffer_state* fb);
void r300_emit_rs_state(struct r300_context* r300, struct r300_rs_state* rs);
void r300_emit_scissor_state(struct r300_context* r300,
struct r300_scissor_state* scissor);

View file

@ -715,20 +715,12 @@ static void r300_set_scissor_state(struct pipe_context* pipe,
struct r300_context* r300 = r300_context(pipe);
draw_flush(r300->draw);
uint32_t left, top, right, bottom;
/* So, a bit of info. The scissors are offset by R300_SCISSORS_OFFSET in
* both directions for all values, and can only be 13 bits wide. Why?
* We may never know. */
left = (state->minx + R300_SCISSORS_OFFSET) & 0x1fff;
top = (state->miny + R300_SCISSORS_OFFSET) & 0x1fff;
right = (state->maxx + R300_SCISSORS_OFFSET) & 0x1fff;
bottom = (state->maxy + R300_SCISSORS_OFFSET) & 0x1fff;
r300->scissor_state->scissor_top_left = (left << R300_SCISSORS_X_SHIFT) |
(top << R300_SCISSORS_Y_SHIFT);
r300->scissor_state->scissor_top_left =
(state->minx << R300_SCISSORS_X_SHIFT) |
(state->miny << R300_SCISSORS_Y_SHIFT);
r300->scissor_state->scissor_bottom_right =
(right << R300_SCISSORS_X_SHIFT) | (bottom << R300_SCISSORS_Y_SHIFT);
(state->maxx << R300_SCISSORS_X_SHIFT) |
(state->maxy << R300_SCISSORS_Y_SHIFT);
r300->dirty_state |= R300_NEW_SCISSOR;
}

View file

@ -54,7 +54,7 @@ static void r300_surface_fill(struct pipe_context* pipe,
return;
}
BEGIN_CS(158 + (caps->is_r500 ? 22 : 14) + (caps->has_tcl ? 4 : 2));
BEGIN_CS(161 + (caps->is_r500 ? 22 : 14) + (caps->has_tcl ? 4 : 2));
/* Flush PVS. */
OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
@ -189,10 +189,16 @@ static void r300_surface_fill(struct pipe_context* pipe,
R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
}
/* The size of the point we're about to draw, in sixths of pixels */
OUT_CS_REG(R300_GA_POINT_SIZE,
((h * 6) & R300_POINTSIZE_Y_MASK) |
((w * 6) << R300_POINTSIZE_X_SHIFT));
/* Pixel scissors */
OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
OUT_CS((x << R300_SCISSORS_X_SHIFT) | (y << R300_SCISSORS_Y_SHIFT));
OUT_CS((w << R300_SCISSORS_X_SHIFT) | (h << R300_SCISSORS_Y_SHIFT));
/* RS block setup */
if (caps->is_r500) {
/* XXX We seem to be in disagreement about how many of these we have