From 47f5d25f93fd36224c112ee2d48e511ae078f8c2 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Thu, 29 May 2025 13:58:33 +0200 Subject: [PATCH] radv,radeonsi: emit UPDATE_DB_SUMMARIZER_TIMEOUT on GFX12 This try to mitigate the HiZ GPU hang by increasing a timeout. Loosely based on PAL but I can confirm it delays the hang when BOTTOM_OF_PIPE_TS is used as a workaround. This must be emitted when the GFX queue is idle. Cc: mesa-stable Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/common/sid.h | 3 +++ src/amd/vulkan/radv_queue.c | 8 ++++++++ src/gallium/drivers/radeonsi/si_state_shaders.cpp | 11 +++++++++++ 3 files changed, 22 insertions(+) diff --git a/src/amd/common/sid.h b/src/amd/common/sid.h index b3e6b4b59a0..9c19d225d29 100644 --- a/src/amd/common/sid.h +++ b/src/amd/common/sid.h @@ -324,6 +324,9 @@ #define S_D10_CACHE_POLICY(x) ((x & 3) << 2) #define S_D10_POLL_INTERVAL(x) ((x & 0xFFFF) << 16) +#define PKT3_UPDATE_DB_SUMMARIZER_TIMEOUT 0xEF /* GFX12+ */ +#define S_EF1_SUMM_CNTL_EVICT_TIMEOUT(x) ((x & 0xFFF) << 0) + #define PKT2_NOP_PAD PKT_TYPE_S(2) #define PKT3_NOP_PAD PKT3(PKT3_NOP, 0x3fff, 0) /* header-only version */ diff --git a/src/amd/vulkan/radv_queue.c b/src/amd/vulkan/radv_queue.c index 4784c965fbb..b8257af05ad 100644 --- a/src/amd/vulkan/radv_queue.c +++ b/src/amd/vulkan/radv_queue.c @@ -700,6 +700,14 @@ radv_emit_ge_rings(struct radv_device *device, struct radeon_cmdbuf *cs, struct S_0309AC_PAF_TEMPORAL(gfx12_store_high_temporal_stay_dirty) | S_0309AC_PAB_TEMPORAL(gfx12_load_last_use_discard) | S_0309AC_SPEC_DATA_READ(gfx12_spec_read_auto) | S_0309AC_FORCE_SE_SCOPE(1) | S_0309AC_PAB_NOFILL(1)); /* R_0309AC_GE_PRIM_RING_SIZE */ + + if (pdev->info.gfx_level == GFX12) { + /* Mitigate the HiZ GPU hang by increasing a timeout when BOTTOM_OF_PIPE_TS is used as the + * workaround. This must be emitted when the gfx queue is idle. + */ + radeon_emit(PKT3(PKT3_UPDATE_DB_SUMMARIZER_TIMEOUT, 0, 0)); + radeon_emit(S_EF1_SUMM_CNTL_EVICT_TIMEOUT(0xfff)); + } } radeon_end(); diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.cpp b/src/gallium/drivers/radeonsi/si_state_shaders.cpp index c19c1d750c4..6dd841219c3 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.cpp +++ b/src/gallium/drivers/radeonsi/si_state_shaders.cpp @@ -5160,6 +5160,17 @@ static void si_emit_spi_ge_ring_state(struct si_context *sctx, unsigned index) S_0309AC_SPEC_DATA_READ(gfx12_spec_read_auto) | S_0309AC_FORCE_SE_SCOPE(1) | S_0309AC_PAB_NOFILL(1)); /* R_0309AC_GE_PRIM_RING_SIZE */ + + if (sctx->gfx_level == GFX12) { + /* Mitigate the HiZ GPU hang by increasing a timeout when + * BOTTOM_OF_PIPE_TS is used as the workaround. This must be + * emitted when the gfx queue is idle. + */ + const uint32_t timeout = sscreen->options.alt_hiz_logic ? 0xfff : 0; + + radeon_emit(PKT3(PKT3_UPDATE_DB_SUMMARIZER_TIMEOUT, 0, 0)); + radeon_emit(S_EF1_SUMM_CNTL_EVICT_TIMEOUT(timeout)); + } } radeon_end(); }