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ac/surface: pass all ac_compute_surface info via ac_surf_config, not radeon_surf

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radeon_surf stops being an input to ac_compute_surface. It's only an output
now.

This makes it clear which fields affect ac_compute_surface.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38093>
This commit is contained in:
Marek Olšák 2025-10-16 06:50:10 -04:00 • committed by Marge Bot
parent 966cb36722
commit 4799dc9447
5 changed files with 109 additions and 17 deletions
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28
src/amd/common/ac_surface.c
View file

@ -3752,9 +3752,33 @@ int ac_compute_surface(struct ac_addrlib *addrlib, const struct radeon_info *inf
const struct ac_surf_config *config, enum radeon_surf_mode mode,
struct radeon_surf *surf)
{
int r;
memset(surf, 0, sizeof(*surf));
r = surf_config_sanity(config, surf->flags);
surf->blk_w = config->blk_w;
surf->blk_h = config->blk_h;
surf->bpe = config->bpe;
surf->flags = config->surf_flags;
surf->modifier = config->modifier;
if (info->gfx_level >= GFX9) {
surf->u.gfx9.swizzle_mode = config->gfx9.swizzle_mode;
surf->u.gfx9.dcc_number_type = config->gfx9.dcc_number_type;
surf->u.gfx9.dcc_data_format = config->gfx9.dcc_data_format;
surf->u.gfx9.color.dcc.max_compressed_block_size = config->gfx9.dcc_max_compressed_block_size;
surf->u.gfx9.color.dcc.independent_64B_blocks = config->gfx9.dcc_independent_64B_blocks;
surf->u.gfx9.color.dcc.independent_128B_blocks = config->gfx9.dcc_independent_128B_blocks;
surf->u.gfx9.dcc_write_compress_disable = config->gfx9.dcc_write_compress_disable;
surf->u.gfx9.color.display_dcc_pitch_max = config->gfx9.display_dcc_pitch_max;
} else {
surf->u.legacy.pipe_config = config->gfx6.pipe_config;
surf->u.legacy.bankw = config->gfx6.bankw;
surf->u.legacy.bankh = config->gfx6.bankh;
surf->u.legacy.tile_split = config->gfx6.tile_split;
surf->u.legacy.mtilea = config->gfx6.mtilea;
surf->u.legacy.num_banks = config->gfx6.num_banks;
}
int r = surf_config_sanity(config, surf->flags);
if (r)
return r;

36
src/amd/common/ac_surface.h
View file

@ -420,10 +420,38 @@ struct ac_surf_info {
struct ac_surf_config {
struct ac_surf_info info;
unsigned is_1d : 1;
unsigned is_3d : 1;
unsigned is_cube : 1;
unsigned is_array : 1;
bool is_1d : 1;
bool is_3d : 1;
bool is_cube : 1;
bool is_array : 1;
uint8_t blk_w : 4; /* block width for block-compressed formats */
uint8_t blk_h : 4; /* block height for block-compressed formats */
uint8_t bpe : 5; /* bytes per element, max 16 */
uint64_t surf_flags; /* bitmask of RADEON_SURF_* */
uint64_t modifier; /* DRM format modifier */
/* For imported images (ac_surface_apply_bo_metadata) and RADEON_SURF_FORCE_SWIZZLE_MODE. */
union {
struct {
unsigned pipe_config : 5; /* max 17 */
unsigned bankw : 4; /* max 8 */
unsigned bankh : 4; /* max 8 */
unsigned tile_split : 13; /* max 4K */
unsigned mtilea : 4; /* max 8 */
unsigned num_banks : 5; /* max 16 */
} gfx6;
struct {
uint8_t swizzle_mode;
uint8_t dcc_number_type; /* GFX12+: CB_COLOR0_INFO.NUMBER_TYPE */
uint8_t dcc_data_format; /* GFX12+: [0:4]:CB_COLOR0_INFO.FORMAT, [5]:MM */
uint8_t dcc_max_compressed_block_size : 2; /* GFX9+ */
bool dcc_independent_64B_blocks : 1; /* GFX9-11 */
bool dcc_independent_128B_blocks : 1; /* GFX9-11 */
bool dcc_write_compress_disable : 1; /* GFX12+ */
uint16_t display_dcc_pitch_max; /* GFX9-11 */
} gfx9;
};
};
/* Output parameters for ac_surface_compute_nbc_view */

11
src/amd/common/ac_surface_modifier_test.c
View file

@ -276,6 +276,10 @@ static void test_modifier(const struct radeon_info *info,
.num_channels = 3,
.array_size = 1
},
.blk_w = 1,
.blk_h = 1,
.bpe = util_format_get_blocksize(format),
.modifier = modifier,
};
struct test_entry entry = {
@ -292,12 +296,7 @@ static void test_modifier(const struct radeon_info *info,
G_0098F8_NUM_PKRS(info->gb_addr_config) : G_0098F8_NUM_BANKS(info->gb_addr_config)
};
struct radeon_surf surf = (struct radeon_surf) {
.blk_w = 1,
.blk_h = 1,
.bpe = util_format_get_blocksize(format),
.modifier = modifier,
};
struct radeon_surf surf;
int r = ac_compute_surface(addrlib, info, &config, RADEON_SURF_MODE_2D, &surf);
assert(!r);

23
src/amd/vulkan/radv_image.c
View file

@ -1103,6 +1103,29 @@ radv_surface_init(struct radv_physical_device *pdev, const struct ac_surf_info *
config.is_3d = type == RADEON_SURF_TYPE_3D;
config.is_cube = type == RADEON_SURF_TYPE_CUBEMAP;
config.is_array = type == RADEON_SURF_TYPE_1D_ARRAY || type == RADEON_SURF_TYPE_2D_ARRAY;
config.blk_w = surf->blk_w;
config.blk_h = surf->blk_h;
config.bpe = surf->bpe;
config.surf_flags = surf->flags;
config.modifier = surf->modifier;
if (pdev->info.gfx_level >= GFX9) {
config.gfx9.swizzle_mode = surf->u.gfx9.swizzle_mode;
config.gfx9.dcc_number_type = surf->u.gfx9.dcc_number_type;
config.gfx9.dcc_data_format = surf->u.gfx9.dcc_data_format;
config.gfx9.dcc_max_compressed_block_size = surf->u.gfx9.color.dcc.max_compressed_block_size;
config.gfx9.dcc_independent_64B_blocks = surf->u.gfx9.color.dcc.independent_64B_blocks;
config.gfx9.dcc_independent_128B_blocks = surf->u.gfx9.color.dcc.independent_128B_blocks;
config.gfx9.dcc_write_compress_disable = surf->u.gfx9.dcc_write_compress_disable;
config.gfx9.display_dcc_pitch_max = surf->u.gfx9.color.display_dcc_pitch_max;
} else {
config.gfx6.pipe_config = surf->u.legacy.pipe_config;
config.gfx6.bankw = surf->u.legacy.bankw;
config.gfx6.bankh = surf->u.legacy.bankh;
config.gfx6.tile_split = surf->u.legacy.tile_split;
config.gfx6.mtilea = surf->u.legacy.mtilea;
config.gfx6.num_banks = surf->u.legacy.num_banks;
}
ac_compute_surface(pdev->addrlib, &pdev->info, &config, mode, surf);
}

28
src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
View file

@ -54,11 +54,6 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
if (r)
return r;
surf->blk_w = util_format_get_blockwidth(tex->format);
surf->blk_h = util_format_get_blockheight(tex->format);
surf->bpe = bpe;
surf->flags = flags;
struct ac_surf_config config;
config.info.width = tex->width0;
@ -76,6 +71,29 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
config.is_array = tex->target == PIPE_TEXTURE_1D_ARRAY ||
tex->target == PIPE_TEXTURE_2D_ARRAY ||
tex->target == PIPE_TEXTURE_CUBE_ARRAY;
config.blk_w = util_format_get_blockwidth(tex->format);
config.blk_h = util_format_get_blockheight(tex->format);
config.bpe = bpe;
config.surf_flags = flags;
config.modifier = surf->modifier;
if (info->gfx_level >= GFX9) {
config.gfx9.swizzle_mode = surf->u.gfx9.swizzle_mode;
config.gfx9.dcc_number_type = surf->u.gfx9.dcc_number_type;
config.gfx9.dcc_data_format = surf->u.gfx9.dcc_data_format;
config.gfx9.dcc_max_compressed_block_size = surf->u.gfx9.color.dcc.max_compressed_block_size;
config.gfx9.dcc_independent_64B_blocks = surf->u.gfx9.color.dcc.independent_64B_blocks;
config.gfx9.dcc_independent_128B_blocks = surf->u.gfx9.color.dcc.independent_128B_blocks;
config.gfx9.dcc_write_compress_disable = surf->u.gfx9.dcc_write_compress_disable;
config.gfx9.display_dcc_pitch_max = surf->u.gfx9.color.display_dcc_pitch_max;
} else {
config.gfx6.pipe_config = surf->u.legacy.pipe_config;
config.gfx6.bankw = surf->u.legacy.bankw;
config.gfx6.bankh = surf->u.legacy.bankh;
config.gfx6.tile_split = surf->u.legacy.tile_split;
config.gfx6.mtilea = surf->u.legacy.mtilea;
config.gfx6.num_banks = surf->u.legacy.num_banks;
}
/* Use radeon_info from the driver, not the winsys. The driver is allowed to change it. */
return ac_compute_surface(aws->addrlib, info, &config, mode, surf);