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radv: clear FMASK layers instead of the whole buffer on GFX8

Browse source 
This reduces the size of fill operations needed to clear FMASK
for layered color textures.

GFX9 unsupported for now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Samuel Pitoiset 2019-06-24 12:18:01 +02:00
parent a5ba386b3f
commit 476b907a3b
8 changed files with 31 additions and 10 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
src/amd/common/ac_surface.c
View file

@ -848,6 +848,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
surf->u.legacy.fmask.tiling_index = fout.tileIndex;
surf->u.legacy.fmask.bankh = fout.pTileInfo->bankHeight;
surf->u.legacy.fmask.pitch_in_pixels = fout.pitch;
surf->u.legacy.fmask.slice_size = fout.sliceSize;
/* Compute tile swizzle for FMASK. */
if (config->info.fmask_surf_index &&

1
src/amd/common/ac_surface.h
View file

@ -86,6 +86,7 @@ struct legacy_surf_fmask {
uint8_t tiling_index; /* max 31 */
uint8_t bankh; /* max 8 */
uint16_t pitch_in_pixels;
uint64_t slice_size;
};
struct legacy_surf_layout {

7
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -4905,7 +4905,8 @@ static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
}
void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image)
struct radv_image *image,
const VkImageSubresourceRange *range)
{
struct radv_cmd_state *state = &cmd_buffer->state;
static const uint32_t fmask_clear_values[4] = {
@ -4920,7 +4921,7 @@ void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
state->flush_bits |= radv_clear_fmask(cmd_buffer, image, value);
state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
}
@ -5008,7 +5009,7 @@ static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
}
if (radv_image_has_fmask(image)) {
radv_initialize_fmask(cmd_buffer, image);
radv_initialize_fmask(cmd_buffer, image, range);
}
if (radv_dcc_enabled(image, range->baseMipLevel)) {

1
src/amd/vulkan/radv_image.c
View file

@ -907,6 +907,7 @@ radv_image_get_fmask_info(struct radv_device *device,
out->slice_tile_max = image->planes[0].surface.u.legacy.fmask.slice_tile_max;
out->tile_mode_index = image->planes[0].surface.u.legacy.fmask.tiling_index;
out->pitch_in_pixels = image->planes[0].surface.u.legacy.fmask.pitch_in_pixels;
out->slice_size = image->planes[0].surface.u.legacy.fmask.slice_size;
out->bank_height = image->planes[0].surface.u.legacy.fmask.bankh;
out->tile_swizzle = image->planes[0].surface.fmask_tile_swizzle;
out->alignment = image->planes[0].surface.fmask_alignment;

3
src/amd/vulkan/radv_meta.h
View file

@ -214,7 +214,8 @@ void radv_decompress_resolve_src(struct radv_cmd_buffer *cmd_buffer,
uint32_t radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image, uint32_t value);
uint32_t radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image, uint32_t value);
struct radv_image *image,
const VkImageSubresourceRange *range, uint32_t value);
uint32_t radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image,
const VkImageSubresourceRange *range, uint32_t value);

22
src/amd/vulkan/radv_meta_clear.c
View file

@ -1336,11 +1336,25 @@ radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
uint32_t
radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image, uint32_t value)
struct radv_image *image,
const VkImageSubresourceRange *range, uint32_t value)
{
return radv_fill_buffer(cmd_buffer, image->bo,
image->offset + image->fmask.offset,
image->fmask.size, value);
uint64_t offset = image->offset + image->fmask.offset;
uint64_t size;
/* MSAA images do not support mipmap levels. */
assert(range->baseMipLevel == 0 &&
radv_get_levelCount(image, range) == 1);
if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
/* TODO: clear layers. */
size = image->fmask.size;
} else {
offset += image->fmask.slice_size * range->baseArrayLayer;
size = image->fmask.slice_size * radv_get_layerCount(image, range);
}
return radv_fill_buffer(cmd_buffer, image->bo, offset, size, value);
}
uint32_t

2
src/amd/vulkan/radv_meta_fmask_expand.c
View file

@ -172,7 +172,7 @@ radv_expand_fmask_image_inplace(struct radv_cmd_buffer *cmd_buffer,
RADV_CMD_FLAG_INV_GLOBAL_L2;
/* Re-initialize FMASK in fully expanded mode. */
radv_initialize_fmask(cmd_buffer, image);
radv_initialize_fmask(cmd_buffer, image, subresourceRange);
}
void radv_device_finish_meta_fmask_expand_state(struct radv_device *device)

4
src/amd/vulkan/radv_private.h
View file

@ -1555,6 +1555,7 @@ struct radv_fmask_info {
unsigned slice_tile_max;
unsigned tile_mode_index;
unsigned tile_swizzle;
uint64_t slice_size;
};
struct radv_cmask_info {
@ -2081,7 +2082,8 @@ void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
const VkImageSubresourceRange *range, uint32_t value);
void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image);
struct radv_image *image,
const VkImageSubresourceRange *range);
struct radv_fence {
struct radeon_winsys_fence *fence;