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ir3: Skip preftech and and warmups for non bindless earlier

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Previously, if only non bindless accesses where present, we would end up
emitting an empty preamble.

Also avoid emitting non binless textures.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40309>
This commit is contained in:
Anna Maniscalco 2026-03-09 19:51:28 +01:00 • committed by Marge Bot
parent 24669f2bbb
commit 47590e0d3e
2 changed files with 9 additions and 4 deletions
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2
src/freedreno/ir3/ir3_compiler_nir.c
View file

@ -3494,8 +3494,6 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
break;
}
case nir_intrinsic_prefetch_ubo_ir3: {
if (!ir3_bindless_resource(intr->src[0]))
break;
struct ir3_instruction *offset = create_immed(b, 0);
struct ir3_instruction *idx = ir3_get_src(ctx, &intr->src[0])[0];
struct ir3_instruction *ldc = ir3_LDC(b, idx, 0, offset, 0);

11
src/freedreno/ir3/ir3_nir_opt_preamble.c
View file

@ -714,6 +714,12 @@ get_preamble_offset(nir_def *def)
return nir_intrinsic_base(nir_def_as_intrinsic(def));
}
static bool
should_prefetch_descriptor(nir_def *desc)
{
return desc != NULL && ir3_bindless_resource(nir_src_for_ssa(desc));
}
/* Prefetch descriptors in the preamble. This is an optimization introduced on
* a7xx, mainly useful when the preamble is an early preamble, and replaces the
* use of CP_LOAD_STATE on a6xx to prefetch descriptors in HLSQ.
@ -765,8 +771,9 @@ ir3_nir_opt_prefetch_descriptors(nir_shader *nir, struct ir3_shader_variant *v)
nir_def *preamble_descs[2] = { NULL, NULL };
get_descriptors(instr, descs);
/* We must have found at least one descriptor */
if (!descs[0] && !descs[1])
/* Bail unless we found at least one bindless descriptor */
if (!(should_prefetch_descriptor(descs[0]) ||
should_prefetch_descriptor(descs[1])))
continue;
/* The instruction itself must be hoistable.