From 47251d28527371aeb82f9db7592cff5e78bfcd55 Mon Sep 17 00:00:00 2001 From: Yusuf Khan Date: Wed, 28 Sep 2022 10:06:33 -0500 Subject: [PATCH] nv50/ir: add prefer_nir flag for getting compiler options So that we dont expose certain options for nir_to_tgsi Signed-off-by: Yusuf Khan Reviewed-by: Karol Herbst Part-of: --- .../drivers/nouveau/nv50/nv50_screen.c | 3 +- .../drivers/nouveau/nvc0/nvc0_screen.c | 2 +- src/nouveau/codegen/nv50_ir_driver.h | 2 +- src/nouveau/codegen/nv50_ir_from_nir.cpp | 97 ++++++++++++++----- 4 files changed, 75 insertions(+), 29 deletions(-) diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c b/src/gallium/drivers/nouveau/nv50/nv50_screen.c index c887c68b3bc..6383a111789 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c @@ -988,8 +988,9 @@ nv50_screen_get_compiler_options(struct pipe_screen *pscreen, enum pipe_shader_ir ir, enum pipe_shader_type shader) { + struct nouveau_screen *screen = nouveau_screen(pscreen); if (ir == PIPE_SHADER_IR_NIR) - return nv50_ir_nir_shader_compiler_options(NVISA_G80_CHIPSET, shader); + return nv50_ir_nir_shader_compiler_options(NVISA_G80_CHIPSET, shader, screen->prefer_nir); return NULL; } diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c index 000f24aa10c..cde717eda31 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c @@ -1020,7 +1020,7 @@ nvc0_screen_get_compiler_options(struct pipe_screen *pscreen, struct nvc0_screen *screen = nvc0_screen(pscreen); if (ir == PIPE_SHADER_IR_NIR) return nv50_ir_nir_shader_compiler_options(screen->base.device->chipset, - shader); + shader, screen->base.prefer_nir); return NULL; } diff --git a/src/nouveau/codegen/nv50_ir_driver.h b/src/nouveau/codegen/nv50_ir_driver.h index 6838c236b99..4988de2b668 100644 --- a/src/nouveau/codegen/nv50_ir_driver.h +++ b/src/nouveau/codegen/nv50_ir_driver.h @@ -220,7 +220,7 @@ extern "C" { #endif const struct nir_shader_compiler_options * -nv50_ir_nir_shader_compiler_options(int chipset, uint8_t shader_type); +nv50_ir_nir_shader_compiler_options(int chipset, uint8_t shader_type, bool prefer_nir); extern int nv50_ir_generate_code(struct nv50_ir_prog_info *, struct nv50_ir_prog_info_out *); diff --git a/src/nouveau/codegen/nv50_ir_from_nir.cpp b/src/nouveau/codegen/nv50_ir_from_nir.cpp index 4550acbf180..74f853b14e5 100644 --- a/src/nouveau/codegen/nv50_ir_from_nir.cpp +++ b/src/nouveau/codegen/nv50_ir_from_nir.cpp @@ -3438,7 +3438,7 @@ Program::makeFromNIR(struct nv50_ir_prog_info *info, } // namespace nv50_ir static nir_shader_compiler_options -nvir_nir_shader_compiler_options(int chipset, uint8_t shader_type) +nvir_nir_shader_compiler_options(int chipset, uint8_t shader_type, bool prefer_nir) { nir_shader_compiler_options op = {}; op.lower_fdiv = (chipset >= NVISA_GV100_CHIPSET); @@ -3560,48 +3560,93 @@ nvir_nir_shader_compiler_options(int chipset, uint8_t shader_type) } static const nir_shader_compiler_options g80_nir_shader_compiler_options = -nvir_nir_shader_compiler_options(NVISA_G80_CHIPSET, PIPE_SHADER_TYPES); +nvir_nir_shader_compiler_options(NVISA_G80_CHIPSET, PIPE_SHADER_TYPES, true); static const nir_shader_compiler_options g80_fs_nir_shader_compiler_options = -nvir_nir_shader_compiler_options(NVISA_G80_CHIPSET, PIPE_SHADER_FRAGMENT); +nvir_nir_shader_compiler_options(NVISA_G80_CHIPSET, PIPE_SHADER_FRAGMENT, true); static const nir_shader_compiler_options gf100_nir_shader_compiler_options = -nvir_nir_shader_compiler_options(NVISA_GF100_CHIPSET, PIPE_SHADER_TYPES); +nvir_nir_shader_compiler_options(NVISA_GF100_CHIPSET, PIPE_SHADER_TYPES, true); static const nir_shader_compiler_options gf100_fs_nir_shader_compiler_options = -nvir_nir_shader_compiler_options(NVISA_GF100_CHIPSET, PIPE_SHADER_FRAGMENT); +nvir_nir_shader_compiler_options(NVISA_GF100_CHIPSET, PIPE_SHADER_FRAGMENT, true); static const nir_shader_compiler_options gm107_nir_shader_compiler_options = -nvir_nir_shader_compiler_options(NVISA_GM107_CHIPSET, PIPE_SHADER_TYPES); +nvir_nir_shader_compiler_options(NVISA_GM107_CHIPSET, PIPE_SHADER_TYPES, true); static const nir_shader_compiler_options gm107_fs_nir_shader_compiler_options = -nvir_nir_shader_compiler_options(NVISA_GM107_CHIPSET, PIPE_SHADER_FRAGMENT); +nvir_nir_shader_compiler_options(NVISA_GM107_CHIPSET, PIPE_SHADER_FRAGMENT, true); static const nir_shader_compiler_options gv100_nir_shader_compiler_options = -nvir_nir_shader_compiler_options(NVISA_GV100_CHIPSET, PIPE_SHADER_TYPES); +nvir_nir_shader_compiler_options(NVISA_GV100_CHIPSET, PIPE_SHADER_TYPES, true); static const nir_shader_compiler_options gv100_fs_nir_shader_compiler_options = -nvir_nir_shader_compiler_options(NVISA_GV100_CHIPSET, PIPE_SHADER_FRAGMENT); +nvir_nir_shader_compiler_options(NVISA_GV100_CHIPSET, PIPE_SHADER_FRAGMENT, true); + +static const nir_shader_compiler_options g80_tgsi_shader_compiler_options = +nvir_nir_shader_compiler_options(NVISA_G80_CHIPSET, PIPE_SHADER_TYPES, false); +static const nir_shader_compiler_options g80_fs_tgsi_shader_compiler_options = +nvir_nir_shader_compiler_options(NVISA_G80_CHIPSET, PIPE_SHADER_FRAGMENT, false); +static const nir_shader_compiler_options gf100_tgsi_shader_compiler_options = +nvir_nir_shader_compiler_options(NVISA_GF100_CHIPSET, PIPE_SHADER_TYPES, false); +static const nir_shader_compiler_options gf100_fs_tgsi_shader_compiler_options = +nvir_nir_shader_compiler_options(NVISA_GF100_CHIPSET, PIPE_SHADER_FRAGMENT, false); +static const nir_shader_compiler_options gm107_tgsi_shader_compiler_options = +nvir_nir_shader_compiler_options(NVISA_GM107_CHIPSET, PIPE_SHADER_TYPES, false); +static const nir_shader_compiler_options gm107_fs_tgsi_shader_compiler_options = +nvir_nir_shader_compiler_options(NVISA_GM107_CHIPSET, PIPE_SHADER_FRAGMENT, false); +static const nir_shader_compiler_options gv100_tgsi_shader_compiler_options = +nvir_nir_shader_compiler_options(NVISA_GV100_CHIPSET, PIPE_SHADER_TYPES, false); +static const nir_shader_compiler_options gv100_fs_tgsi_shader_compiler_options = +nvir_nir_shader_compiler_options(NVISA_GV100_CHIPSET, PIPE_SHADER_FRAGMENT, false); const nir_shader_compiler_options * -nv50_ir_nir_shader_compiler_options(int chipset, uint8_t shader_type) +nv50_ir_nir_shader_compiler_options(int chipset, uint8_t shader_type, bool prefer_nir) { if (chipset >= NVISA_GV100_CHIPSET) { - if (shader_type == PIPE_SHADER_FRAGMENT) - return &gv100_fs_nir_shader_compiler_options; - else - return &gv100_nir_shader_compiler_options; + if (shader_type == PIPE_SHADER_FRAGMENT) { + if (prefer_nir) + return &gv100_fs_nir_shader_compiler_options; + else + return &gv100_fs_tgsi_shader_compiler_options; + } else { + if (prefer_nir) + return &gv100_nir_shader_compiler_options; + else + return &gv100_tgsi_shader_compiler_options; + } } if (chipset >= NVISA_GM107_CHIPSET) { - if (shader_type == PIPE_SHADER_FRAGMENT) - return &gm107_fs_nir_shader_compiler_options; - else - return &gm107_nir_shader_compiler_options; + if (shader_type == PIPE_SHADER_FRAGMENT) { + if (prefer_nir) + return &gm107_fs_nir_shader_compiler_options; + else + return &gm107_fs_tgsi_shader_compiler_options; + } else { + if (prefer_nir) + return &gm107_nir_shader_compiler_options; + else + return &gm107_tgsi_shader_compiler_options; + } } if (chipset >= NVISA_GF100_CHIPSET) { - if (shader_type == PIPE_SHADER_FRAGMENT) - return &gf100_fs_nir_shader_compiler_options; - else - return &gf100_nir_shader_compiler_options; + if (shader_type == PIPE_SHADER_FRAGMENT) { + if (prefer_nir) + return &gf100_fs_nir_shader_compiler_options; + else + return &gf100_fs_tgsi_shader_compiler_options; + } else { + if (prefer_nir) + return &gf100_nir_shader_compiler_options; + else + return &gf100_tgsi_shader_compiler_options; + } } - if (shader_type == PIPE_SHADER_FRAGMENT) - return &g80_fs_nir_shader_compiler_options; - else - return &g80_nir_shader_compiler_options; + if (shader_type == PIPE_SHADER_FRAGMENT) { + if (prefer_nir) + return &g80_fs_nir_shader_compiler_options; + else + return &g80_fs_tgsi_shader_compiler_options; + } else { + if (prefer_nir) + return &g80_nir_shader_compiler_options; + else + return &g80_tgsi_shader_compiler_options; + } }