From 47251b2e2dc2097d1530b3def064dd56d545482c Mon Sep 17 00:00:00 2001 From: Danylo Piliaiev Date: Thu, 12 Feb 2026 19:56:35 +0100 Subject: [PATCH] ir3: Align TCS per-patch output to 64 bytes to prevent stale reads Empirically, TCS outputs have to be aligned to 64 bytes, otherwise stale data may be read in rare cases. The exact reason is not clear, but tests and proprietary driver behavior strongly point at the need for 64 byte alignment. Fixes tesselation issues in at least "Conan Exiles" but likely in many more cases. CC: mesa-stable Signed-off-by: Danylo Piliaiev Part-of: --- src/freedreno/ir3/ir3_nir_lower_tess.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/freedreno/ir3/ir3_nir_lower_tess.c b/src/freedreno/ir3/ir3_nir_lower_tess.c index b44237080d2..3de73558227 100644 --- a/src/freedreno/ir3/ir3_nir_lower_tess.c +++ b/src/freedreno/ir3/ir3_nir_lower_tess.c @@ -662,7 +662,13 @@ ir3_nir_lower_tess_ctrl(nir_shader *shader, struct ir3_shader_variant *v, build_primitive_map(shader, &state.map); memcpy(v->output_loc, state.map.loc, sizeof(v->output_loc)); - v->output_size = state.map.stride; + + /* Empirically, TCS outputs have to be aligned to 64 bytes, + * otherwise stale data may be read in rare cases. The exact + * reason is not clear, but tests and proprietary driver behavior + * strongly point at the need for 64 byte alignment. + */ + v->output_size = ALIGN_POT(state.map.stride, 16); nir_function_impl *impl = nir_shader_get_entrypoint(shader); assert(impl);