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ac/gpu_info: add AMD_CU_MASK environment variable to set CU_EN
requested internally Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14122>
This commit is contained in:
Marek Olšák
parent
a68cb9db8d
commit
470b61f3a9
2 changed files with 157 additions and 2 deletions
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@ -24,12 +24,15 @@
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*/
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#include "ac_gpu_info.h"
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#include "ac_shader_util.h"
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#include "addrlib/src/amdgpu_asic_addr.h"
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#include "sid.h"
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#include "util/macros.h"
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#include "util/u_cpu_detect.h"
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#include "util/u_math.h"
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#include "util/os_misc.h"
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#include "util/bitset.h"
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#include <stdio.h>
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#include <ctype.h>
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@ -330,6 +333,151 @@ has_tmz_support(amdgpu_device_handle dev,
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return true;
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}
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static void set_custom_cu_en_mask(struct radeon_info *info)
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{
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info->spi_cu_en = ~0;
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const char *cu_env_var = os_get_option("AMD_CU_MASK");
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if (!cu_env_var)
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return;
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int size = strlen(cu_env_var);
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char *str = alloca(size + 1);
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memset(str, 0, size + 1);
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size = 0;
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/* Strip whitespace. */
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for (unsigned src = 0; cu_env_var[src]; src++) {
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if (cu_env_var[src] != ' ' && cu_env_var[src] != '\t' &&
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cu_env_var[src] != '\n' && cu_env_var[src] != '\r') {
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str[size++] = cu_env_var[src];
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}
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}
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/* The following syntax is used, all whitespace is ignored:
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* ID = [0-9][0-9]* ex. base 10 numbers
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* ID_list = (ID | ID-ID)[, (ID | ID-ID)]* ex. 0,2-4,7
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* CU_list = 0x[0-F]* | ID_list ex. 0x337F OR 0,2-4,7
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* AMD_CU_MASK = CU_list
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*
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* It's a CU mask within a shader array. It's applied to all shader arrays.
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*/
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bool is_good_form = true;
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uint32_t spi_cu_en = 0;
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if (size > 2 && str[0] == '0' && (str[1] == 'x' || str[1] == 'X')) {
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str += 2;
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size -= 2;
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for (unsigned i = 0; i < size; i++)
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is_good_form &= isxdigit(str[i]) != 0;
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if (!is_good_form) {
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fprintf(stderr, "amd: invalid AMD_CU_MASK: ill-formed hex value\n");
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} else {
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spi_cu_en = strtol(str, NULL, 16);
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}
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} else {
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/* Parse ID_list. */
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long first = 0, last = -1;
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if (!isdigit(*str)) {
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is_good_form = false;
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} else {
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while (*str) {
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bool comma = false;
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if (isdigit(*str)) {
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first = last = strtol(str, &str, 10);
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} else if (*str == '-') {
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str++;
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/* Parse a digit after a dash. */
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if (isdigit(*str)) {
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last = strtol(str, &str, 10);
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} else {
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fprintf(stderr, "amd: invalid AMD_CU_MASK: expected a digit after -\n");
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is_good_form = false;
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break;
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}
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} else if (*str == ',') {
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comma = true;
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str++;
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if (!isdigit(*str)) {
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fprintf(stderr, "amd: invalid AMD_CU_MASK: expected a digit after ,\n");
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is_good_form = false;
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break;
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}
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}
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if (comma || !*str) {
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if (first > last) {
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fprintf(stderr, "amd: invalid AMD_CU_MASK: range not increasing (%li, %li)\n", first, last);
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is_good_form = false;
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break;
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}
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if (last > 31) {
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fprintf(stderr, "amd: invalid AMD_CU_MASK: index too large (%li)\n", last);
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is_good_form = false;
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break;
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}
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spi_cu_en |= BITFIELD_RANGE(first, last - first + 1);
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last = -1;
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}
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}
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}
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}
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/* The mask is parsed. Now assign bits to CUs. */
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if (is_good_form) {
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bool error = false;
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/* Clear bits that have no effect. */
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spi_cu_en &= BITFIELD_MASK(info->max_good_cu_per_sa);
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if (!spi_cu_en) {
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fprintf(stderr, "amd: invalid AMD_CU_MASK: at least 1 CU in each SA must be enabled\n");
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error = true;
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}
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if (info->has_graphics) {
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uint32_t min_full_cu_mask = BITFIELD_MASK(info->min_good_cu_per_sa);
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/* The hw ignores all non-compute CU masks if any of them is 0. Disallow that. */
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if ((spi_cu_en & min_full_cu_mask) == 0) {
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fprintf(stderr, "amd: invalid AMD_CU_MASK: at least 1 CU from 0x%x per SA must be "
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"enabled (SPI limitation)\n", min_full_cu_mask);
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error = true;
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}
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/* We usually disable 1 or 2 CUs for VS and GS, which means at last 1 other CU
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* must be enabled.
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*/
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uint32_t cu_mask_ge, unused;
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ac_compute_late_alloc(info, false, false, false, &unused, &cu_mask_ge);
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cu_mask_ge &= min_full_cu_mask;
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if ((spi_cu_en & cu_mask_ge) == 0) {
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fprintf(stderr, "amd: invalid AMD_CU_MASK: at least 1 CU from 0x%x per SA must be "
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"enabled (late alloc constraint for GE)\n", cu_mask_ge);
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error = true;
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}
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if ((min_full_cu_mask & spi_cu_en & ~cu_mask_ge) == 0) {
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fprintf(stderr, "amd: invalid AMD_CU_MASK: at least 1 CU from 0x%x per SA must be "
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"enabled (late alloc constraint for PS)\n",
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min_full_cu_mask & ~cu_mask_ge);
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error = true;
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}
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}
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if (!error) {
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info->spi_cu_en = spi_cu_en;
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info->spi_cu_en_has_effect = spi_cu_en & BITFIELD_MASK(info->max_good_cu_per_sa);
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}
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}
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}
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bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
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struct amdgpu_gpu_info *amdinfo)
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@ -1095,6 +1243,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
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info->num_physical_wave64_vgprs_per_simd = info->chip_class >= GFX10 ? 512 : 256;
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info->num_simd_per_compute_unit = info->chip_class >= GFX10 ? 2 : 4;
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set_custom_cu_en_mask(info);
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return true;
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}
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@ -1253,10 +1402,12 @@ void ac_print_gpu_info(struct radeon_info *info, FILE *f)
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fprintf(f, "Shader core info:\n");
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for (unsigned i = 0; i < info->max_se; i++) {
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for (unsigned j = 0; j < info->max_sa_per_se; j++) {
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fprintf(f, " cu_mask[SE%u][SA%u] = 0x%x \t(%u)\n",
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i, j, info->cu_mask[i][j], util_bitcount(info->cu_mask[i][j]));
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fprintf(f, " cu_mask[SE%u][SA%u] = 0x%x \t(%u)\tCU_EN = 0x%x\n", i, j,
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info->cu_mask[i][j], util_bitcount(info->cu_mask[i][j]),
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info->spi_cu_en & BITFIELD_MASK(util_bitcount(info->cu_mask[i][j])));
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}
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}
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fprintf(f, " spi_cu_en_has_effect = %i\n", info->spi_cu_en_has_effect);
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fprintf(f, " max_shader_clock = %i\n", info->max_shader_clock);
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fprintf(f, " num_good_compute_units = %i\n", info->num_good_compute_units);
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fprintf(f, " max_good_cu_per_sa = %i\n", info->max_good_cu_per_sa);
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@ -232,6 +232,10 @@ struct radeon_info {
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/* Tile modes. */
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uint32_t si_tile_mode_array[32];
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uint32_t cik_macrotile_mode_array[16];
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/* AMD_CU_MASK environment variable or ~0. */
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bool spi_cu_en_has_effect;
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uint32_t spi_cu_en;
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};
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bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
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