diff --git a/src/freedreno/.gitlab-ci/reference/crash.log b/src/freedreno/.gitlab-ci/reference/crash.log index 62c387c88d8..3ca89220612 100644 --- a/src/freedreno/.gitlab-ci/reference/crash.log +++ b/src/freedreno/.gitlab-ci/reference/crash.log @@ -1612,10 +1612,10 @@ registers: 00000000 0x8e76: 00000000 00000000 0x8e77: 00000000 00000000 HLSQ_UNKNOWN_BE00: 0 - 00000001 HLSQ_UNKNOWN_BE01: 0x1 + 00000001 HLSQ_UNKNOWN_BE01: 0 | 0x1 00000004 HLSQ_UNKNOWN_BE04: 0x4 00000000 HLSQ_ADDR_MODE_CNTL: ADDR_32B - deadbeef 0xbe08: deadbeef + deadbeef HLSQ_UNKNOWN_BE08: 0xbeef | 0xdead0000 deadbeef 0xbe09: deadbeef 00000000 HLSQ_PERFCTR_HLSQ_SEL[0]+0: 00000000 00000000 HLSQ_PERFCTR_HLSQ_SEL[0x1]+0: 00000000 @@ -1675,10 +1675,10 @@ registers: deadbeef 0xae50: deadbeef deadbeef 0xae51: deadbeef deadbeef 0xae52: deadbeef - 00000000 SP_UNKNOWN_B600: 0 + 00000000 TPL1_UNKNOWN_B600: 0 00000001 TPL1_ADDR_MODE_CNTL: ADDR_64B - 00000004 TPL1_NC_MODE_CNTL: 0x4 - 00000000 SP_UNKNOWN_B605: 0 + 00000004 TPL1_NC_MODE_CNTL: { LOWER_BIT = 2 | UPPER_BIT = 0 } + 00000000 TPL1_UNKNOWN_B605: 0 00000000 TPL1_PERFCTR_TP_SEL[0]+0: 00000000 00000000 TPL1_PERFCTR_TP_SEL[0x1]+0: 00000000 00000000 TPL1_PERFCTR_TP_SEL[0x2]+0: 00000000 @@ -6343,9 +6343,9 @@ clusters: 00000000 VFD_CONTROL_0: { FETCH_CNT = 0 | DECODE_CNT = 0 } fcfcfcfc VFD_CONTROL_1: { REGID4VTX = r63.x | REGID4INST = r63.x | REGID4PRIMID = r63.x | REGID4VIEWID = r63.x } 0000fcfc VFD_CONTROL_2: { REGID_HSPATCHID = r63.x | REGID_INVOCATIONID = r63.x } - fcfcfcfc VFD_CONTROL_3: { REGID_DSPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x | 0xfc } - 000000fc VFD_CONTROL_4: 0xfc - 0000fcfc VFD_CONTROL_5: { REGID_GSHEADER = r63.x | 0xfc00 } + fcfcfcfc VFD_CONTROL_3: { UNK0 = r63.x | REGID_DSPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 000000fc VFD_CONTROL_4: { UNK0 = r63.x } + 0000fcfc VFD_CONTROL_5: { REGID_GSHEADER = r63.x | UNK8 = r63.x } 00000000 VFD_CONTROL_6: { 0 } 00000000 VFD_MODE_CNTL: { 0 } 00000000 VFD_MULTIVIEW_CNTL: { VIEWS = 0 } @@ -6481,69 +6481,69 @@ clusters: 01810080 VFD_FETCH[0x1f].SIZE: 25231488 00000020 VFD_FETCH[0x1f].STRIDE: 32 00002320 VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0x119 | FORMAT = 0 | SWAP = WZYX } - 4698e051 VFD_DECODE[0].STEP_RATE: 0x4698e051 + 4698e051 VFD_DECODE[0].STEP_RATE: 1184424017 00000000 VFD_DECODE[0x1].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = 0 | SWAP = WZYX } - 00400015 VFD_DECODE[0x1].STEP_RATE: 0x400015 + 00400015 VFD_DECODE[0x1].STEP_RATE: 4194325 00002400 VFD_DECODE[0x2].INSTR: { IDX = 0 | OFFSET = 0x120 | FORMAT = 0 | SWAP = WZYX } - 0228c300 VFD_DECODE[0x2].STEP_RATE: 0x228c300 + 0228c300 VFD_DECODE[0x2].STEP_RATE: 36225792 00008040 VFD_DECODE[0x3].INSTR: { IDX = 0 | OFFSET = 0x402 | FORMAT = 0 | SWAP = WZYX } - 40804000 VFD_DECODE[0x3].STEP_RATE: 0x40804000 + 40804000 VFD_DECODE[0x3].STEP_RATE: 1082146816 00000180 VFD_DECODE[0x4].INSTR: { IDX = 0 | OFFSET = 0xc | FORMAT = 0 | SWAP = WZYX } - 20801028 VFD_DECODE[0x4].STEP_RATE: 0x20801028 + 20801028 VFD_DECODE[0x4].STEP_RATE: 545263656 00002800 VFD_DECODE[0x5].INSTR: { IDX = 0 | OFFSET = 0x140 | FORMAT = 0 | SWAP = WZYX } - 50004104 VFD_DECODE[0x5].STEP_RATE: 0x50004104 + 50004104 VFD_DECODE[0x5].STEP_RATE: 1342193924 00000040 VFD_DECODE[0x6].INSTR: { IDX = 0 | OFFSET = 0x2 | FORMAT = 0 | SWAP = WZYX } - c9708400 VFD_DECODE[0x6].STEP_RATE: 0xc9708400 + c9708400 VFD_DECODE[0x6].STEP_RATE: 3379594240 00008a00 VFD_DECODE[0x7].INSTR: { IDX = 0 | OFFSET = 0x450 | FORMAT = 0 | SWAP = WZYX } - 00000180 VFD_DECODE[0x7].STEP_RATE: 0x180 + 00000180 VFD_DECODE[0x7].STEP_RATE: 384 00018910 VFD_DECODE[0x8].INSTR: { IDX = 16 | OFFSET = 0xc48 | FORMAT = 0 | SWAP = WZYX } - 00202080 VFD_DECODE[0x8].STEP_RATE: 0x202080 + 00202080 VFD_DECODE[0x8].STEP_RATE: 2105472 00000200 VFD_DECODE[0x9].INSTR: { IDX = 0 | OFFSET = 0x10 | FORMAT = 0 | SWAP = WZYX } - 10000400 VFD_DECODE[0x9].STEP_RATE: 0x10000400 + 10000400 VFD_DECODE[0x9].STEP_RATE: 268436480 00019180 VFD_DECODE[0xa].INSTR: { IDX = 0 | OFFSET = 0xc8c | FORMAT = 0 | SWAP = WZYX } - 00010881 VFD_DECODE[0xa].STEP_RATE: 0x10881 + 00010881 VFD_DECODE[0xa].STEP_RATE: 67713 00002200 VFD_DECODE[0xb].INSTR: { IDX = 0 | OFFSET = 0x110 | FORMAT = 0 | SWAP = WZYX } - 00000008 VFD_DECODE[0xb].STEP_RATE: 0x8 + 00000008 VFD_DECODE[0xb].STEP_RATE: 8 00000090 VFD_DECODE[0xc].INSTR: { IDX = 16 | OFFSET = 0x4 | FORMAT = 0 | SWAP = WZYX } - 00108040 VFD_DECODE[0xc].STEP_RATE: 0x108040 + 00108040 VFD_DECODE[0xc].STEP_RATE: 1081408 00002002 VFD_DECODE[0xd].INSTR: { IDX = 2 | OFFSET = 0x100 | FORMAT = 0 | SWAP = WZYX } - 40040004 VFD_DECODE[0xd].STEP_RATE: 0x40040004 + 40040004 VFD_DECODE[0xd].STEP_RATE: 1074003972 00000000 VFD_DECODE[0xe].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = 0 | SWAP = WZYX } - 00418202 VFD_DECODE[0xe].STEP_RATE: 0x418202 + 00418202 VFD_DECODE[0xe].STEP_RATE: 4293122 00011200 VFD_DECODE[0xf].INSTR: { IDX = 0 | OFFSET = 0x890 | FORMAT = 0 | SWAP = WZYX } - 05000504 VFD_DECODE[0xf].STEP_RATE: 0x5000504 + 05000504 VFD_DECODE[0xf].STEP_RATE: 83887364 00002002 VFD_DECODE[0x10].INSTR: { IDX = 2 | OFFSET = 0x100 | FORMAT = 0 | SWAP = WZYX } - 20210026 VFD_DECODE[0x10].STEP_RATE: 0x20210026 + 20210026 VFD_DECODE[0x10].STEP_RATE: 539033638 00000008 VFD_DECODE[0x11].INSTR: { IDX = 8 | OFFSET = 0 | FORMAT = 0 | SWAP = WZYX } - 00010400 VFD_DECODE[0x11].STEP_RATE: 0x10400 + 00010400 VFD_DECODE[0x11].STEP_RATE: 66560 00009000 VFD_DECODE[0x12].INSTR: { IDX = 0 | OFFSET = 0x480 | FORMAT = 0 | SWAP = WZYX } 00000000 VFD_DECODE[0x12].STEP_RATE: 0 00002000 VFD_DECODE[0x13].INSTR: { IDX = 0 | OFFSET = 0x100 | FORMAT = 0 | SWAP = WZYX } - 10080000 VFD_DECODE[0x13].STEP_RATE: 0x10080000 + 10080000 VFD_DECODE[0x13].STEP_RATE: 268959744 00001200 VFD_DECODE[0x14].INSTR: { IDX = 0 | OFFSET = 0x90 | FORMAT = 0 | SWAP = WZYX } - 20048020 VFD_DECODE[0x14].STEP_RATE: 0x20048020 + 20048020 VFD_DECODE[0x14].STEP_RATE: 537165856 00000106 VFD_DECODE[0x15].INSTR: { IDX = 6 | OFFSET = 0x8 | FORMAT = 0 | SWAP = WZYX } - 0a200812 VFD_DECODE[0x15].STEP_RATE: 0xa200812 + 0a200812 VFD_DECODE[0x15].STEP_RATE: 169871378 00008042 VFD_DECODE[0x16].INSTR: { IDX = 2 | OFFSET = 0x402 | FORMAT = 0 | SWAP = WZYX } - 00140250 VFD_DECODE[0x16].STEP_RATE: 0x140250 + 00140250 VFD_DECODE[0x16].STEP_RATE: 1311312 00008080 VFD_DECODE[0x17].INSTR: { IDX = 0 | OFFSET = 0x404 | FORMAT = 0 | SWAP = WZYX } - 120000c0 VFD_DECODE[0x17].STEP_RATE: 0x120000c0 + 120000c0 VFD_DECODE[0x17].STEP_RATE: 301990080 00000482 VFD_DECODE[0x18].INSTR: { IDX = 2 | OFFSET = 0x24 | FORMAT = 0 | SWAP = WZYX } - 00400880 VFD_DECODE[0x18].STEP_RATE: 0x400880 + 00400880 VFD_DECODE[0x18].STEP_RATE: 4196480 00002000 VFD_DECODE[0x19].INSTR: { IDX = 0 | OFFSET = 0x100 | FORMAT = 0 | SWAP = WZYX } - 00201000 VFD_DECODE[0x19].STEP_RATE: 0x201000 + 00201000 VFD_DECODE[0x19].STEP_RATE: 2101248 00000000 VFD_DECODE[0x1a].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = 0 | SWAP = WZYX } - 40000802 VFD_DECODE[0x1a].STEP_RATE: 0x40000802 + 40000802 VFD_DECODE[0x1a].STEP_RATE: 1073743874 00000028 VFD_DECODE[0x1b].INSTR: { IDX = 8 | OFFSET = 0x1 | FORMAT = 0 | SWAP = WZYX } - 0020a120 VFD_DECODE[0x1b].STEP_RATE: 0x20a120 + 0020a120 VFD_DECODE[0x1b].STEP_RATE: 2138400 00012480 VFD_DECODE[0x1c].INSTR: { IDX = 0 | OFFSET = 0x924 | FORMAT = 0 | SWAP = WZYX } - 09004200 VFD_DECODE[0x1c].STEP_RATE: 0x9004200 + 09004200 VFD_DECODE[0x1c].STEP_RATE: 151011840 00008080 VFD_DECODE[0x1d].INSTR: { IDX = 0 | OFFSET = 0x404 | FORMAT = 0 | SWAP = WZYX } - 00004004 VFD_DECODE[0x1d].STEP_RATE: 0x4004 + 00004004 VFD_DECODE[0x1d].STEP_RATE: 16388 00010888 VFD_DECODE[0x1e].INSTR: { IDX = 8 | OFFSET = 0x844 | FORMAT = 0 | SWAP = WZYX } - 000000b4 VFD_DECODE[0x1e].STEP_RATE: 0xb4 + 000000b4 VFD_DECODE[0x1e].STEP_RATE: 180 00008000 VFD_DECODE[0x1f].INSTR: { IDX = 0 | OFFSET = 0x400 | FORMAT = 0 | SWAP = WZYX } - 04800000 VFD_DECODE[0x1f].STEP_RATE: 0x4800000 + 04800000 VFD_DECODE[0x1f].STEP_RATE: 75497472 00000445 VFD_DEST_CNTL[0].INSTR: { WRITEMASK = 0x5 | REGID = r17.x } 00000004 VFD_DEST_CNTL[0x1].INSTR: { WRITEMASK = 0x4 | REGID = r0.x } 00000804 VFD_DEST_CNTL[0x2].INSTR: { WRITEMASK = 0x4 | REGID = r32.x } @@ -6603,9 +6603,9 @@ clusters: 00000000 VFD_CONTROL_0: { FETCH_CNT = 0 | DECODE_CNT = 0 } fcfcfcfc VFD_CONTROL_1: { REGID4VTX = r63.x | REGID4INST = r63.x | REGID4PRIMID = r63.x | REGID4VIEWID = r63.x } 0000fcfc VFD_CONTROL_2: { REGID_HSPATCHID = r63.x | REGID_INVOCATIONID = r63.x } - fcfcfcfc VFD_CONTROL_3: { REGID_DSPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x | 0xfc } - 000000fc VFD_CONTROL_4: 0xfc - 0000fcfc VFD_CONTROL_5: { REGID_GSHEADER = r63.x | 0xfc00 } + fcfcfcfc VFD_CONTROL_3: { UNK0 = r63.x | REGID_DSPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 000000fc VFD_CONTROL_4: { UNK0 = r63.x } + 0000fcfc VFD_CONTROL_5: { REGID_GSHEADER = r63.x | UNK8 = r63.x } 00000000 VFD_CONTROL_6: { 0 } 00000000 VFD_MODE_CNTL: { 0 } 00000000 VFD_MULTIVIEW_CNTL: { VIEWS = 0 } @@ -6741,69 +6741,69 @@ clusters: 01810080 VFD_FETCH[0x1f].SIZE: 25231488 00000020 VFD_FETCH[0x1f].STRIDE: 32 00002320 VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0x119 | FORMAT = 0 | SWAP = WZYX } - 4698e051 VFD_DECODE[0].STEP_RATE: 0x4698e051 + 4698e051 VFD_DECODE[0].STEP_RATE: 1184424017 00000000 VFD_DECODE[0x1].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = 0 | SWAP = WZYX } - 00400015 VFD_DECODE[0x1].STEP_RATE: 0x400015 + 00400015 VFD_DECODE[0x1].STEP_RATE: 4194325 00002400 VFD_DECODE[0x2].INSTR: { IDX = 0 | OFFSET = 0x120 | FORMAT = 0 | SWAP = WZYX } - 0228c300 VFD_DECODE[0x2].STEP_RATE: 0x228c300 + 0228c300 VFD_DECODE[0x2].STEP_RATE: 36225792 00008040 VFD_DECODE[0x3].INSTR: { IDX = 0 | OFFSET = 0x402 | FORMAT = 0 | SWAP = WZYX } - 40804000 VFD_DECODE[0x3].STEP_RATE: 0x40804000 + 40804000 VFD_DECODE[0x3].STEP_RATE: 1082146816 00000180 VFD_DECODE[0x4].INSTR: { IDX = 0 | OFFSET = 0xc | FORMAT = 0 | SWAP = WZYX } - 20801028 VFD_DECODE[0x4].STEP_RATE: 0x20801028 + 20801028 VFD_DECODE[0x4].STEP_RATE: 545263656 00002800 VFD_DECODE[0x5].INSTR: { IDX = 0 | OFFSET = 0x140 | FORMAT = 0 | SWAP = WZYX } - 50004104 VFD_DECODE[0x5].STEP_RATE: 0x50004104 + 50004104 VFD_DECODE[0x5].STEP_RATE: 1342193924 00000040 VFD_DECODE[0x6].INSTR: { IDX = 0 | OFFSET = 0x2 | FORMAT = 0 | SWAP = WZYX } - c9708400 VFD_DECODE[0x6].STEP_RATE: 0xc9708400 + c9708400 VFD_DECODE[0x6].STEP_RATE: 3379594240 00008a00 VFD_DECODE[0x7].INSTR: { IDX = 0 | OFFSET = 0x450 | FORMAT = 0 | SWAP = WZYX } - 00000180 VFD_DECODE[0x7].STEP_RATE: 0x180 + 00000180 VFD_DECODE[0x7].STEP_RATE: 384 00018910 VFD_DECODE[0x8].INSTR: { IDX = 16 | OFFSET = 0xc48 | FORMAT = 0 | SWAP = WZYX } - 00202080 VFD_DECODE[0x8].STEP_RATE: 0x202080 + 00202080 VFD_DECODE[0x8].STEP_RATE: 2105472 00000200 VFD_DECODE[0x9].INSTR: { IDX = 0 | OFFSET = 0x10 | FORMAT = 0 | SWAP = WZYX } - 10000400 VFD_DECODE[0x9].STEP_RATE: 0x10000400 + 10000400 VFD_DECODE[0x9].STEP_RATE: 268436480 00019180 VFD_DECODE[0xa].INSTR: { IDX = 0 | OFFSET = 0xc8c | FORMAT = 0 | SWAP = WZYX } - 00010881 VFD_DECODE[0xa].STEP_RATE: 0x10881 + 00010881 VFD_DECODE[0xa].STEP_RATE: 67713 00002200 VFD_DECODE[0xb].INSTR: { IDX = 0 | OFFSET = 0x110 | FORMAT = 0 | SWAP = WZYX } - 00000008 VFD_DECODE[0xb].STEP_RATE: 0x8 + 00000008 VFD_DECODE[0xb].STEP_RATE: 8 00000090 VFD_DECODE[0xc].INSTR: { IDX = 16 | OFFSET = 0x4 | FORMAT = 0 | SWAP = WZYX } - 00108040 VFD_DECODE[0xc].STEP_RATE: 0x108040 + 00108040 VFD_DECODE[0xc].STEP_RATE: 1081408 00002002 VFD_DECODE[0xd].INSTR: { IDX = 2 | OFFSET = 0x100 | FORMAT = 0 | SWAP = WZYX } - 40040004 VFD_DECODE[0xd].STEP_RATE: 0x40040004 + 40040004 VFD_DECODE[0xd].STEP_RATE: 1074003972 00000000 VFD_DECODE[0xe].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = 0 | SWAP = WZYX } - 00418202 VFD_DECODE[0xe].STEP_RATE: 0x418202 + 00418202 VFD_DECODE[0xe].STEP_RATE: 4293122 00011200 VFD_DECODE[0xf].INSTR: { IDX = 0 | OFFSET = 0x890 | FORMAT = 0 | SWAP = WZYX } - 05000504 VFD_DECODE[0xf].STEP_RATE: 0x5000504 + 05000504 VFD_DECODE[0xf].STEP_RATE: 83887364 00002002 VFD_DECODE[0x10].INSTR: { IDX = 2 | OFFSET = 0x100 | FORMAT = 0 | SWAP = WZYX } - 20210026 VFD_DECODE[0x10].STEP_RATE: 0x20210026 + 20210026 VFD_DECODE[0x10].STEP_RATE: 539033638 00000008 VFD_DECODE[0x11].INSTR: { IDX = 8 | OFFSET = 0 | FORMAT = 0 | SWAP = WZYX } - 00010400 VFD_DECODE[0x11].STEP_RATE: 0x10400 + 00010400 VFD_DECODE[0x11].STEP_RATE: 66560 00009000 VFD_DECODE[0x12].INSTR: { IDX = 0 | OFFSET = 0x480 | FORMAT = 0 | SWAP = WZYX } 00000000 VFD_DECODE[0x12].STEP_RATE: 0 00002000 VFD_DECODE[0x13].INSTR: { IDX = 0 | OFFSET = 0x100 | FORMAT = 0 | SWAP = WZYX } - 10080000 VFD_DECODE[0x13].STEP_RATE: 0x10080000 + 10080000 VFD_DECODE[0x13].STEP_RATE: 268959744 00001200 VFD_DECODE[0x14].INSTR: { IDX = 0 | OFFSET = 0x90 | FORMAT = 0 | SWAP = WZYX } - 20048020 VFD_DECODE[0x14].STEP_RATE: 0x20048020 + 20048020 VFD_DECODE[0x14].STEP_RATE: 537165856 00000106 VFD_DECODE[0x15].INSTR: { IDX = 6 | OFFSET = 0x8 | FORMAT = 0 | SWAP = WZYX } - 0a200812 VFD_DECODE[0x15].STEP_RATE: 0xa200812 + 0a200812 VFD_DECODE[0x15].STEP_RATE: 169871378 00008042 VFD_DECODE[0x16].INSTR: { IDX = 2 | OFFSET = 0x402 | FORMAT = 0 | SWAP = WZYX } - 00140250 VFD_DECODE[0x16].STEP_RATE: 0x140250 + 00140250 VFD_DECODE[0x16].STEP_RATE: 1311312 00008080 VFD_DECODE[0x17].INSTR: { IDX = 0 | OFFSET = 0x404 | FORMAT = 0 | SWAP = WZYX } - 120000c0 VFD_DECODE[0x17].STEP_RATE: 0x120000c0 + 120000c0 VFD_DECODE[0x17].STEP_RATE: 301990080 00000482 VFD_DECODE[0x18].INSTR: { IDX = 2 | OFFSET = 0x24 | FORMAT = 0 | SWAP = WZYX } - 00400880 VFD_DECODE[0x18].STEP_RATE: 0x400880 + 00400880 VFD_DECODE[0x18].STEP_RATE: 4196480 00002000 VFD_DECODE[0x19].INSTR: { IDX = 0 | OFFSET = 0x100 | FORMAT = 0 | SWAP = WZYX } - 00201000 VFD_DECODE[0x19].STEP_RATE: 0x201000 + 00201000 VFD_DECODE[0x19].STEP_RATE: 2101248 00000000 VFD_DECODE[0x1a].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = 0 | SWAP = WZYX } - 40000802 VFD_DECODE[0x1a].STEP_RATE: 0x40000802 + 40000802 VFD_DECODE[0x1a].STEP_RATE: 1073743874 00000028 VFD_DECODE[0x1b].INSTR: { IDX = 8 | OFFSET = 0x1 | FORMAT = 0 | SWAP = WZYX } - 0020a120 VFD_DECODE[0x1b].STEP_RATE: 0x20a120 + 0020a120 VFD_DECODE[0x1b].STEP_RATE: 2138400 00012480 VFD_DECODE[0x1c].INSTR: { IDX = 0 | OFFSET = 0x924 | FORMAT = 0 | SWAP = WZYX } - 09004200 VFD_DECODE[0x1c].STEP_RATE: 0x9004200 + 09004200 VFD_DECODE[0x1c].STEP_RATE: 151011840 00008080 VFD_DECODE[0x1d].INSTR: { IDX = 0 | OFFSET = 0x404 | FORMAT = 0 | SWAP = WZYX } - 00004004 VFD_DECODE[0x1d].STEP_RATE: 0x4004 + 00004004 VFD_DECODE[0x1d].STEP_RATE: 16388 00010888 VFD_DECODE[0x1e].INSTR: { IDX = 8 | OFFSET = 0x844 | FORMAT = 0 | SWAP = WZYX } - 000000b4 VFD_DECODE[0x1e].STEP_RATE: 0xb4 + 000000b4 VFD_DECODE[0x1e].STEP_RATE: 180 00008000 VFD_DECODE[0x1f].INSTR: { IDX = 0 | OFFSET = 0x400 | FORMAT = 0 | SWAP = WZYX } - 04800000 VFD_DECODE[0x1f].STEP_RATE: 0x4800000 + 04800000 VFD_DECODE[0x1f].STEP_RATE: 75497472 00000445 VFD_DEST_CNTL[0].INSTR: { WRITEMASK = 0x5 | REGID = r17.x } 00000004 VFD_DEST_CNTL[0x1].INSTR: { WRITEMASK = 0x4 | REGID = r0.x } 00000804 VFD_DEST_CNTL[0x2].INSTR: { WRITEMASK = 0x4 | REGID = r32.x } @@ -6900,7 +6900,7 @@ clusters: 00000100 HLSQ_GS_CNTL: { CONSTLEN = 0 | ENABLED } 40204000 HLSQ_LOAD_STATE_GEOM_CMD: 0x40204000 00000000 HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR: 0 - 00000000 HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR+0x1: 0 + 00000000 HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR_HI: 0 - context: 1 00000140 HLSQ_VS_CNTL: { CONSTLEN = 256 | ENABLED } 00000000 HLSQ_HS_CNTL: { CONSTLEN = 0 } @@ -6908,12 +6908,12 @@ clusters: 00000100 HLSQ_GS_CNTL: { CONSTLEN = 0 | ENABLED } 40204000 HLSQ_LOAD_STATE_GEOM_CMD: 0x40204000 00000000 HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR: 0 - 00000000 HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR+0x1: 0 + 00000000 HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR_HI: 0 - cluster-name: CLUSTER_SP_VS - context: 0 - 00000000 SP_VS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = THREAD64 } + 00000000 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = THREAD64 } 00000000 SP_VS_BRANCH_COND: 0 - 00000000 SP_VS_PRIMITIVE_CNTL: { OUT = 0 } + 00000000 SP_VS_PRIMITIVE_CNTL: { OUT = 0 | FLAGS_REGID = r0.x } 00000000 SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } @@ -6948,9 +6948,9 @@ clusters: 00000080 SP_VS_TEX_COUNT: 128 00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } 00000000 SP_VS_INSTRLEN: 0 - 00000000 SP_HS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = THREAD64 } + 00000000 SP_HS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = THREAD64 } 00000000 SP_HS_WAVE_INPUT_SIZE: 0 - 00000000 0xa832: 00000000 + 00000000 SP_HS_BRANCH_COND: 0 00000000 SP_HS_OBJ_FIRST_EXEC_OFFSET: 0 780a8ca5 SP_HS_OBJ_START: 0x780a8ca5 0001aad2 SP_HS_OBJ_START_HI: 0x1aad2 @@ -6961,9 +6961,9 @@ clusters: 00000080 SP_HS_TEX_COUNT: 128 00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } 00000000 SP_HS_INSTRLEN: 0 - 00000000 SP_DS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = THREAD64 } - 00000000 0xa841: 00000000 - 00000000 SP_DS_PRIMITIVE_CNTL: { OUT = 0 } + 00000000 SP_DS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = THREAD64 } + 00000000 SP_DS_BRANCH_COND: 0 + 00000000 SP_DS_PRIMITIVE_CNTL: { OUT = 0 | FLAGS_REGID = r0.x } 00000000 SP_DS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } 00000000 SP_DS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } 00000000 SP_DS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } @@ -6998,7 +6998,7 @@ clusters: 00000080 SP_DS_TEX_COUNT: 128 00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } 00000000 SP_DS_INSTRLEN: 0 - 00000000 SP_GS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = THREAD64 } + 00000000 SP_GS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = THREAD64 } 00000000 SP_GS_PRIM_SIZE: 0 00000000 SP_GS_BRANCH_COND: 0 00000000 SP_GS_PRIMITIVE_CNTL: { OUT = 0 | FLAGS_REGID = r0.x } @@ -7057,9 +7057,9 @@ clusters: 00000000 0xa8c2: 00000000 00000000 0xa8c3: 00000000 - context: 1 - 00000000 SP_VS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = THREAD64 } + 00000000 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = THREAD64 } 00000000 SP_VS_BRANCH_COND: 0 - 00000000 SP_VS_PRIMITIVE_CNTL: { OUT = 0 } + 00000000 SP_VS_PRIMITIVE_CNTL: { OUT = 0 | FLAGS_REGID = r0.x } 00000000 SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } @@ -7094,9 +7094,9 @@ clusters: 00000080 SP_VS_TEX_COUNT: 128 00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } 00000000 SP_VS_INSTRLEN: 0 - 00000000 SP_HS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = THREAD64 } + 00000000 SP_HS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = THREAD64 } 00000000 SP_HS_WAVE_INPUT_SIZE: 0 - 00000000 0xa832: 00000000 + 00000000 SP_HS_BRANCH_COND: 0 00000000 SP_HS_OBJ_FIRST_EXEC_OFFSET: 0 780a8ca5 SP_HS_OBJ_START: 0x780a8ca5 0001aad2 SP_HS_OBJ_START_HI: 0x1aad2 @@ -7107,9 +7107,9 @@ clusters: 00000080 SP_HS_TEX_COUNT: 128 00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } 00000000 SP_HS_INSTRLEN: 0 - 00000000 SP_DS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = THREAD64 } - 00000000 0xa841: 00000000 - 00000000 SP_DS_PRIMITIVE_CNTL: { OUT = 0 } + 00000000 SP_DS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = THREAD64 } + 00000000 SP_DS_BRANCH_COND: 0 + 00000000 SP_DS_PRIMITIVE_CNTL: { OUT = 0 | FLAGS_REGID = r0.x } 00000000 SP_DS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } 00000000 SP_DS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } 00000000 SP_DS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } @@ -7144,7 +7144,7 @@ clusters: 00000080 SP_DS_TEX_COUNT: 128 00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } 00000000 SP_DS_INSTRLEN: 0 - 00000000 SP_GS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = THREAD64 } + 00000000 SP_GS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = THREAD64 } 00000000 SP_GS_PRIM_SIZE: 0 00000000 SP_GS_BRANCH_COND: 0 00000000 SP_GS_PRIMITIVE_CNTL: { OUT = 0 | FLAGS_REGID = r0.x } @@ -7279,7 +7279,7 @@ clusters: 00000000 SP_TP_SAMPLE_LOCATION_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } 00000000 SP_TP_SAMPLE_LOCATION_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } 00000000 SP_TP_WINDOW_OFFSET: { X = 0 | Y = 0 } - 0000004c SP_TP_UNKNOWN_B309: 0x4c + 0000004c SP_TP_UNKNOWN_B309: 76 deadbeef 0xb380: deadbeef deadbeef 0xb381: deadbeef deadbeef 0xb382: deadbeef @@ -7292,7 +7292,7 @@ clusters: 00000000 SP_TP_SAMPLE_LOCATION_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } 00000000 SP_TP_SAMPLE_LOCATION_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } 00000000 SP_TP_WINDOW_OFFSET: { X = 0 | Y = 0 } - 0000004c SP_TP_UNKNOWN_B309: 0x4c + 0000004c SP_TP_UNKNOWN_B309: 76 deadbeef 0xb380: deadbeef deadbeef 0xb381: deadbeef deadbeef 0xb382: deadbeef @@ -7303,7 +7303,7 @@ clusters: fcfcfcfc HLSQ_CONTROL_2_REG: { FACEREGID = r63.x | SAMPLEID = r63.x | SAMPLEMASK = r63.x | SIZE = r63.x } fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } fcfcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | XYCOORDREGID = r63.x | ZWCOORDREGID = r63.x } - 000000fc HLSQ_CONTROL_5_REG: 0xfc + 000000fc HLSQ_CONTROL_5_REG: { UNK0 = r63.x } 00000101 HLSQ_CS_CNTL: { CONSTLEN = 4 | ENABLED } 000003fd HLSQ_CS_NDRANGE_0: { KERNELDIM = 1 | LOCALSIZEX = 255 | LOCALSIZEY = 0 | LOCALSIZEZ = 0 } 00000200 HLSQ_CS_NDRANGE_1: { GLOBALSIZE_X = 512 } @@ -7319,7 +7319,7 @@ clusters: 00000001 HLSQ_CS_KERNEL_GROUP_Z: 0x1 40304000 HLSQ_LOAD_STATE_FRAG_CMD: 0x40304000 8c415430 HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR: 0x8c415430 - 00000000 HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR+0x1: 0 + 00000000 HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR_HI: 0 00000000 HLSQ_CS_BINDLESS_BASE[0].ADDR: 0 00000000 HLSQ_CS_BINDLESS_BASE[0].ADDR_HI: 0 00000000 HLSQ_CS_BINDLESS_BASE[0x1].ADDR: 0 @@ -7336,7 +7336,7 @@ clusters: fcfcfcfc HLSQ_CONTROL_2_REG: { FACEREGID = r63.x | SAMPLEID = r63.x | SAMPLEMASK = r63.x | SIZE = r63.x } fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } fcfcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | XYCOORDREGID = r63.x | ZWCOORDREGID = r63.x } - 000000fc HLSQ_CONTROL_5_REG: 0xfc + 000000fc HLSQ_CONTROL_5_REG: { UNK0 = r63.x } 00000101 HLSQ_CS_CNTL: { CONSTLEN = 4 | ENABLED } 000003fd HLSQ_CS_NDRANGE_0: { KERNELDIM = 1 | LOCALSIZEX = 255 | LOCALSIZEY = 0 | LOCALSIZEZ = 0 } 00000200 HLSQ_CS_NDRANGE_1: { GLOBALSIZE_X = 512 } @@ -7352,7 +7352,7 @@ clusters: 00000001 HLSQ_CS_KERNEL_GROUP_Z: 0x1 40304000 HLSQ_LOAD_STATE_FRAG_CMD: 0x40304000 8c415430 HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR: 0x8c415430 - 00000000 HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR+0x1: 0 + 00000000 HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR_HI: 0 00000000 HLSQ_CS_BINDLESS_BASE[0].ADDR: 0 00000000 HLSQ_CS_BINDLESS_BASE[0].ADDR_HI: 0 00000000 HLSQ_CS_BINDLESS_BASE[0x1].ADDR: 0 @@ -7370,7 +7370,7 @@ clusters: deadbeef HLSQ_2D_EVENT_CMD: { STATE_ID = 0xbe | EVENT = 0x6f | 0xdead0080 } - cluster-name: CLUSTER_SP_PS - context: 0 - 05100000 SP_FS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = THREAD128 | PIXLODENABLE | 0x1000000 } + 05100000 SP_FS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = THREAD128 | UNK24 | PIXLODENABLE } 00000000 SP_FS_BRANCH_COND: 0 00000000 SP_FS_OBJ_FIRST_EXEC_OFFSET: 0 4bdb43d8 SP_FS_OBJ_START: 0x4bdb43d8 @@ -7411,9 +7411,9 @@ clusters: 00000000 SP_FS_BINDLESS_PREFETCH[0x3].CMD: { SAMP_ID = 0 | TEX_ID = 0 } 00000080 SP_FS_TEX_COUNT: 128 0000f000 SP_UNKNOWN_A9A8: 0xf000 - 00421800 SP_CS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 48 | BRANCHSTACK = 8 | THREADSIZE = THREAD64 | VARYING } - 0000001f SP_CS_UNKNOWN_A9B1: 31 - 00000000 0xa9b2: 00000000 + 00421800 SP_CS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 48 | BRANCHSTACK = 8 | THREADSIZE = THREAD64 | VARYING } + 0000001f SP_CS_UNKNOWN_A9B1: { SHARED_SIZE_2K | UNK1 = 0xf } + 00000000 SP_CS_BRANCH_COND: 0 00000000 SP_CS_OBJ_FIRST_EXEC_OFFSET: 0 8c415420 SP_CS_OBJ_START: 0x8c415420 00000000 SP_CS_OBJ_START_HI: 0 @@ -7452,7 +7452,7 @@ clusters: 00000000 0xaa30: 00000000 00000000 0xaa31: 00000000 - context: 1 - 05100000 SP_FS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = THREAD128 | PIXLODENABLE | 0x1000000 } + 05100000 SP_FS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = THREAD128 | UNK24 | PIXLODENABLE } 00000000 SP_FS_BRANCH_COND: 0 00000000 SP_FS_OBJ_FIRST_EXEC_OFFSET: 0 4bdb43d8 SP_FS_OBJ_START: 0x4bdb43d8 @@ -7493,9 +7493,9 @@ clusters: 00000000 SP_FS_BINDLESS_PREFETCH[0x3].CMD: { SAMP_ID = 0 | TEX_ID = 0 } 00000080 SP_FS_TEX_COUNT: 128 0000f000 SP_UNKNOWN_A9A8: 0xf000 - 00421800 SP_CS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 48 | BRANCHSTACK = 8 | THREADSIZE = THREAD64 | VARYING } - 0000001f SP_CS_UNKNOWN_A9B1: 31 - 00000000 0xa9b2: 00000000 + 00421800 SP_CS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 48 | BRANCHSTACK = 8 | THREADSIZE = THREAD64 | VARYING } + 0000001f SP_CS_UNKNOWN_A9B1: { SHARED_SIZE_2K | UNK1 = 0xf } + 00000000 SP_CS_BRANCH_COND: 0 00000000 SP_CS_OBJ_FIRST_EXEC_OFFSET: 0 8c415420 SP_CS_OBJ_START: 0x8c415420 00000000 SP_CS_OBJ_START_HI: 0 @@ -7544,15 +7544,15 @@ clusters: 00000000 SP_PS_TP_BORDER_COLOR_BASE_ADDR_HI: 0 00000000 SP_UNKNOWN_B182: 0 00000000 SP_UNKNOWN_B183: 0 - 00000000 0xb190: 00000000 - 00000000 0xb191: 00000000 + 00000000 SP_UNKNOWN_B190: 0 + 00000000 SP_UNKNOWN_B191: 0 - context: 1 00000000 SP_PS_TP_BORDER_COLOR_BASE_ADDR: 0 00000000 SP_PS_TP_BORDER_COLOR_BASE_ADDR_HI: 0 00000000 SP_UNKNOWN_B182: 0 00000000 SP_UNKNOWN_B183: 0 - 00000000 0xb190: 00000000 - 00000000 0xb191: 00000000 + 00000000 SP_UNKNOWN_B190: 0 + 00000000 SP_UNKNOWN_B191: 0 - cluster-name: CLUSTER_SP_PS - context: 0 00000000 SP_PS_2D_SRC_INFO: { COLOR_FORMAT = 0 | TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX | SAMPLES = MSAA_ONE } @@ -7560,18 +7560,18 @@ clusters: 00000000 SP_PS_2D_SRC: 0 00000000 SP_PS_2D_SRC_HI: 0 00000000 SP_PS_2D_SRC_PITCH: { PITCH = 0 } - 00000000 0xb4c5: 00000000 - 00000000 0xb4c6: 00000000 - 00000000 0xb4c7: 00000000 - 00000000 0xb4c8: 00000000 - 00000000 0xb4c9: 00000000 + 00000000 SP_PS_2D_SRC_PLANE1: 0 + 00000000 SP_PS_2D_SRC_PLANE1_HI: 0 + 00000000 SP_PS_2D_SRC_PLANE_PITCH: 0 + 00000000 SP_PS_2D_SRC_PLANE2: 0 + 00000000 SP_PS_2D_SRC_PLANE2_HI: 0 00000000 SP_PS_2D_SRC_FLAGS: 0 00000000 SP_PS_2D_SRC_FLAGS_HI: 0 - 00000000 SP_PS_2D_SRC_FLAGS_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } - 00000000 0xb4cd: 00000000 - 00000000 0xb4ce: 00000000 - 00000000 0xb4cf: 00000000 - 00000000 0xb4d0: 00000000 + 00000000 SP_PS_2D_SRC_FLAGS_PITCH: 0 + 00000000 SP_PS_UNKNOWN_B4CD: 0 + 00000000 SP_PS_UNKNOWN_B4CE: 0 + 00000000 SP_PS_UNKNOWN_B4CF: 0 + 00000000 SP_PS_UNKNOWN_B4D0: 0 00000000 SP_WINDOW_OFFSET: { X = 0 | Y = 0 } - context: 1 00000000 SP_PS_2D_SRC_INFO: { COLOR_FORMAT = 0 | TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX | SAMPLES = MSAA_ONE } @@ -7579,18 +7579,18 @@ clusters: 00000000 SP_PS_2D_SRC: 0 00000000 SP_PS_2D_SRC_HI: 0 00000000 SP_PS_2D_SRC_PITCH: { PITCH = 0 } - 00000000 0xb4c5: 00000000 - 00000000 0xb4c6: 00000000 - 00000000 0xb4c7: 00000000 - 00000000 0xb4c8: 00000000 - 00000000 0xb4c9: 00000000 + 00000000 SP_PS_2D_SRC_PLANE1: 0 + 00000000 SP_PS_2D_SRC_PLANE1_HI: 0 + 00000000 SP_PS_2D_SRC_PLANE_PITCH: 0 + 00000000 SP_PS_2D_SRC_PLANE2: 0 + 00000000 SP_PS_2D_SRC_PLANE2_HI: 0 00000000 SP_PS_2D_SRC_FLAGS: 0 00000000 SP_PS_2D_SRC_FLAGS_HI: 0 - 00000000 SP_PS_2D_SRC_FLAGS_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } - 00000000 0xb4cd: 00000000 - 00000000 0xb4ce: 00000000 - 00000000 0xb4cf: 00000000 - 00000000 0xb4d0: 00000000 + 00000000 SP_PS_2D_SRC_FLAGS_PITCH: 0 + 00000000 SP_PS_UNKNOWN_B4CD: 0 + 00000000 SP_PS_UNKNOWN_B4CE: 0 + 00000000 SP_PS_UNKNOWN_B4CF: 0 + 00000000 SP_PS_UNKNOWN_B4D0: 0 00000000 SP_WINDOW_OFFSET: { X = 0 | Y = 0 } - cluster-name: CLUSTER_SP_PS - context: 0 @@ -7664,7 +7664,7 @@ clusters: 00000000 SP_TP_SAMPLE_LOCATION_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } 00000000 SP_TP_SAMPLE_LOCATION_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } 00000000 SP_TP_WINDOW_OFFSET: { X = 0 | Y = 0 } - 0000004c SP_TP_UNKNOWN_B309: 0x4c + 0000004c SP_TP_UNKNOWN_B309: 76 deadbeef 0xb380: deadbeef deadbeef 0xb381: deadbeef deadbeef 0xb382: deadbeef @@ -7677,7 +7677,7 @@ clusters: 00000000 SP_TP_SAMPLE_LOCATION_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } 00000000 SP_TP_SAMPLE_LOCATION_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } 00000000 SP_TP_WINDOW_OFFSET: { X = 0 | Y = 0 } - 0000004c SP_TP_UNKNOWN_B309: 0x4c + 0000004c SP_TP_UNKNOWN_B309: 76 deadbeef 0xb380: deadbeef deadbeef 0xb381: deadbeef deadbeef 0xb382: deadbeef diff --git a/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log b/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log index ae1f482193a..00938a135b0 100644 --- a/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log +++ b/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log @@ -27,11 +27,11 @@ t4 write SP_UNKNOWN_AE00 (ae00) t4 write SP_PERFCTR_ENABLE (ae0f) SP_PERFCTR_ENABLE: { VS | HS | DS | GS | FS | CS } 0000000001058034: 0000: 40ae0f01 0000003f -t4 write SP_UNKNOWN_B605 (b605) - SP_UNKNOWN_B605: 0x44 +t4 write TPL1_UNKNOWN_B605 (b605) + TPL1_UNKNOWN_B605: 68 000000000105803c: 0000: 40b60501 00000044 -t4 write SP_UNKNOWN_B600 (b600) - SP_UNKNOWN_B600: 0x100000 +t4 write TPL1_UNKNOWN_B600 (b600) + TPL1_UNKNOWN_B600: 0x100000 0000000001058044: 0000: 40b60001 00100000 t4 write HLSQ_UNKNOWN_BE00 (be00) HLSQ_UNKNOWN_BE00: 0x80 @@ -76,7 +76,7 @@ t4 write SP_UNKNOWN_A9A8 (a9a8) SP_UNKNOWN_A9A8: 0 00000000010580b4: 0000: 40a9a801 00000000 t4 write SP_MODE_CONTROL (ab00) - SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | 0x4 } + SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | UNK2 } 00000000010580bc: 0000: 40ab0001 00000005 t4 write VFD_ADD_OFFSET (a009) VFD_ADD_OFFSET: { VERTEX } @@ -175,10 +175,10 @@ t4 write PC_UNKNOWN_9E72 (9e72) PC_UNKNOWN_9E72: 0 00000000010581bc: 0000: 409e7201 00000000 t4 write SP_TP_UNKNOWN_B309 (b309) - SP_TP_UNKNOWN_B309: 0xa2 + SP_TP_UNKNOWN_B309: 162 00000000010581c4: 0000: 40b30901 000000a2 t4 write HLSQ_CONTROL_5_REG (b986) - HLSQ_CONTROL_5_REG: 0xfc + HLSQ_CONTROL_5_REG: { UNK0 = r63.x } 00000000010581cc: 0000: 48b98601 000000fc t4 write VFD_MODE_CNTL (a007) VFD_MODE_CNTL: { 0 } @@ -195,10 +195,10 @@ t7 opcode: CP_SET_DRAW_STATE (43) (4 dwords) { ADDR_HI = 0 } 00000000010581ec: 0000: 70438003 00040000 00000000 00000000 t4 write SP_HS_CTRL_REG0 (a830) - SP_HS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = THREAD64 } + SP_HS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = THREAD64 } 00000000010581fc: 0000: 40a83001 00000000 t4 write SP_GS_CTRL_REG0 (a870) - SP_GS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = THREAD64 } + SP_GS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = THREAD64 } 0000000001058204: 0000: 48a87001 00000000 t4 write GRAS_LRZ_CNTL (8100) GRAS_LRZ_CNTL: { 0 } @@ -341,11 +341,11 @@ t7 opcode: CP_BLIT (2c) (2 dwords) + 00000000 VFD_MULTIVIEW_CNTL: { VIEWS = 0 } !+ 00000001 VFD_ADD_OFFSET: { VERTEX } + 00000000 SP_VS_OBJ_FIRST_EXEC_OFFSET: 0 - + 00000000 SP_HS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = THREAD64 } - + 00000000 SP_GS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = THREAD64 } + + 00000000 SP_HS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = THREAD64 } + + 00000000 SP_GS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = THREAD64 } + 00000000 SP_FS_OBJ_FIRST_EXEC_OFFSET: 0 + 00000000 SP_UNKNOWN_A9A8: 0 -!+ 00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | 0x4 } +!+ 00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | UNK2 } + 00000000 SP_IBO_COUNT: 0 !+ 0000f180 SP_2D_DST_FORMAT: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf } + 00000000 SP_UNKNOWN_AE00: 0 @@ -358,10 +358,10 @@ t7 opcode: CP_BLIT (2c) (2 dwords) + 00000000 SP_UNKNOWN_B183: 0 !+ 01011000 SP_TP_BORDER_COLOR_BASE_ADDR: 0x1011000 + 00000000 SP_TP_BORDER_COLOR_BASE_ADDR_HI: 0 -!+ 000000a2 SP_TP_UNKNOWN_B309: 0xa2 -!+ 00100000 SP_UNKNOWN_B600: 0x100000 -!+ 00000044 SP_UNKNOWN_B605: 0x44 -!+ 000000fc HLSQ_CONTROL_5_REG: 0xfc +!+ 000000a2 SP_TP_UNKNOWN_B309: 162 +!+ 00100000 TPL1_UNKNOWN_B600: 0x100000 +!+ 00000044 TPL1_UNKNOWN_B605: 68 +!+ 000000fc HLSQ_CONTROL_5_REG: { UNK0 = r63.x } !+ 000fffff HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_IBO | GFX_IBO | CS_SHARED_CONST | GFX_SHARED_CONST | CS_BINDLESS = 0x1f | GFX_BINDLESS = 0x1f } + 00000000 HLSQ_SHARED_CONSTS: { 0 } !+ 00000080 HLSQ_UNKNOWN_BE00: 0x80 @@ -783,7 +783,7 @@ t4 write HLSQ_INVALIDATE_CMD (bb08) HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | GFX_IBO | CS_BINDLESS = 0 | GFX_BINDLESS = 0 } 0000000001054180: 0000: 40bb0801 0000009f t4 write SP_VS_CTRL_REG0 (a800) - SP_VS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 3 | BRANCHSTACK = 0 | THREADSIZE = THREAD128 | MERGEDREGS } + SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 3 | BRANCHSTACK = 0 | THREADSIZE = THREAD128 | MERGEDREGS } 0000000001054188: 0000: 40a80001 80100180 t4 write SP_VS_CONFIG (a823) SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } @@ -863,7 +863,7 @@ t4 write HLSQ_GS_CNTL (b803) HLSQ_GS_CNTL: { CONSTLEN = 0 } 0000000001054208: 0000: 48b80301 00000000 t4 write SP_FS_CTRL_REG0 (a980) - SP_FS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | BRANCHSTACK = 0 | THREADSIZE = THREAD128 | VARYING | MERGEDREGS | 0x1000000 } + SP_FS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | BRANCHSTACK = 0 | THREADSIZE = THREAD128 | VARYING | UNK24 | MERGEDREGS } 0000000001054210: 0000: 40a98001 81500100 t4 write SP_FS_CONFIG (ab04) SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } @@ -926,9 +926,9 @@ t4 write SP_HS_WAVE_INPUT_SIZE (a831) t4 write VFD_CONTROL_1 (a001) VFD_CONTROL_1: { REGID4VTX = r2.y | REGID4INST = r63.x | REGID4PRIMID = r63.x | REGID4VIEWID = r63.x } VFD_CONTROL_2: { REGID_HSPATCHID = r63.x | REGID_INVOCATIONID = r63.x } - VFD_CONTROL_3: { REGID_DSPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x | 0xfc } - VFD_CONTROL_4: 0xfc - VFD_CONTROL_5: { REGID_GSHEADER = r63.x | 0xfc00 } + VFD_CONTROL_3: { UNK0 = r63.x | REGID_DSPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + VFD_CONTROL_4: { UNK0 = r63.x } + VFD_CONTROL_5: { REGID_GSHEADER = r63.x | UNK8 = r63.x } VFD_CONTROL_6: { 0 } 0000000001054260: 0000: 40a00186 fcfcfc09 0000fcfc fcfcfcfc 000000fc 0000fcfc 00000000 t4 write VPC_VAR[0].DISABLE (9212) @@ -960,7 +960,7 @@ t4 write PC_VS_OUT_CNTL (9b01) PC_VS_OUT_CNTL: { STRIDE_IN_VPC = 8 | CLIP_MASK = 0 } 00000000010542cc: 0000: 489b0101 00000008 t4 write SP_VS_PRIMITIVE_CNTL (a802) - SP_VS_PRIMITIVE_CNTL: { OUT = 2 } + SP_VS_PRIMITIVE_CNTL: { OUT = 2 | FLAGS_REGID = r0.x } 00000000010542d4: 0000: 48a80201 00000002 t4 write VPC_VS_LAYER_CNTL (9104) VPC_VS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 } @@ -997,14 +997,14 @@ t4 write VPC_VARYING_PS_REPL[0].MODE (9208) 0000000001054320: 0000: 48920808 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t4 write SP_FS_PREFETCH_CNTL (a99e) - SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK4 = r63.x | 0x7000 } + SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK4 = r63.x | UNK12 = 0x7 } 0000000001054344: 0000: 40a99e01 00007fc0 t4 write HLSQ_CONTROL_1_REG (b982) HLSQ_CONTROL_1_REG: 0x7 HLSQ_CONTROL_2_REG: { FACEREGID = r63.x | SAMPLEID = r63.x | SAMPLEMASK = r63.x | SIZE = r63.x } HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | XYCOORDREGID = r63.x | ZWCOORDREGID = r63.x } - HLSQ_CONTROL_5_REG: 0xfc + HLSQ_CONTROL_5_REG: { UNK0 = r63.x } 000000000105434c: 0000: 40b98285 00000007 fcfcfcfc fcfcfc00 fcfcfcfc 000000fc t4 write HLSQ_FS_CNTL_0 (b980) HLSQ_FS_CNTL_0: { THREADSIZE = THREAD128 | VARYINGS } @@ -1087,21 +1087,21 @@ t4 write VFD_FETCH[0].STRIDE (a013) 0000000001054620: 0000: 40a01301 00000024 t4 write VFD_DECODE[0].INSTR (a090) VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = FMT6_32_32_32_32_FLOAT | SWAP = WZYX | UNK30 | FLOAT } - VFD_DECODE[0].STEP_RATE: 0x1 + VFD_DECODE[0].STEP_RATE: 1 0000000001054628: 0000: 48a09002 c8200000 00000001 t4 write VFD_DEST_CNTL[0].INSTR (a0d0) VFD_DEST_CNTL[0].INSTR: { WRITEMASK = 0xf | REGID = r0.x } 0000000001054634: 0000: 40a0d001 0000000f t4 write VFD_DECODE[0x1].INSTR (a092) VFD_DECODE[0x1].INSTR: { IDX = 0 | OFFSET = 0x10 | FORMAT = FMT6_32_32_32_32_FLOAT | SWAP = WZYX | UNK30 | FLOAT } - VFD_DECODE[0x1].STEP_RATE: 0x1 + VFD_DECODE[0x1].STEP_RATE: 1 000000000105463c: 0000: 40a09202 c8200200 00000001 t4 write VFD_DEST_CNTL[0x1].INSTR (a0d1) VFD_DEST_CNTL[0x1].INSTR: { WRITEMASK = 0xf | REGID = r1.x } 0000000001054648: 0000: 48a0d101 0000004f t4 write VFD_DECODE[0x2].INSTR (a094) VFD_DECODE[0x2].INSTR: { IDX = 0 | OFFSET = 0x20 | FORMAT = FMT6_32_SINT | SWAP = WZYX | UNK30 } - VFD_DECODE[0x2].STEP_RATE: 0x1 + VFD_DECODE[0x2].STEP_RATE: 1 0000000001054650: 0000: 40a09402 44c00400 00000001 t4 write VFD_DEST_CNTL[0x2].INSTR (a0d2) VFD_DEST_CNTL[0x2].INSTR: { WRITEMASK = 0x1 | REGID = r2.x } @@ -1430,25 +1430,25 @@ t7 opcode: CP_DRAW_INDIRECT_MULTI (2a) (12 dwords) !+ 00000303 VFD_CONTROL_0: { FETCH_CNT = 3 | DECODE_CNT = 3 } !+ fcfcfc09 VFD_CONTROL_1: { REGID4VTX = r2.y | REGID4INST = r63.x | REGID4PRIMID = r63.x | REGID4VIEWID = r63.x } !+ 0000fcfc VFD_CONTROL_2: { REGID_HSPATCHID = r63.x | REGID_INVOCATIONID = r63.x } -!+ fcfcfcfc VFD_CONTROL_3: { REGID_DSPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x | 0xfc } -!+ 000000fc VFD_CONTROL_4: 0xfc -!+ 0000fcfc VFD_CONTROL_5: { REGID_GSHEADER = r63.x | 0xfc00 } +!+ fcfcfcfc VFD_CONTROL_3: { UNK0 = r63.x | REGID_DSPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } +!+ 000000fc VFD_CONTROL_4: { UNK0 = r63.x } +!+ 0000fcfc VFD_CONTROL_5: { REGID_GSHEADER = r63.x | UNK8 = r63.x } + 00000000 VFD_CONTROL_6: { 0 } !+ 01053000 VFD_FETCH[0].BASE: 0x1053000 + 00000000 VFD_FETCH[0].BASE_HI: 0 !+ 00000318 VFD_FETCH[0].SIZE: 792 !+ 00000024 VFD_FETCH[0].STRIDE: 36 !+ c8200000 VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = FMT6_32_32_32_32_FLOAT | SWAP = WZYX | UNK30 | FLOAT } -!+ 00000001 VFD_DECODE[0].STEP_RATE: 0x1 +!+ 00000001 VFD_DECODE[0].STEP_RATE: 1 !+ c8200200 VFD_DECODE[0x1].INSTR: { IDX = 0 | OFFSET = 0x10 | FORMAT = FMT6_32_32_32_32_FLOAT | SWAP = WZYX | UNK30 | FLOAT } -!+ 00000001 VFD_DECODE[0x1].STEP_RATE: 0x1 +!+ 00000001 VFD_DECODE[0x1].STEP_RATE: 1 !+ 44c00400 VFD_DECODE[0x2].INSTR: { IDX = 0 | OFFSET = 0x20 | FORMAT = FMT6_32_SINT | SWAP = WZYX | UNK30 } -!+ 00000001 VFD_DECODE[0x2].STEP_RATE: 0x1 +!+ 00000001 VFD_DECODE[0x2].STEP_RATE: 1 !+ 0000000f VFD_DEST_CNTL[0].INSTR: { WRITEMASK = 0xf | REGID = r0.x } !+ 0000004f VFD_DEST_CNTL[0x1].INSTR: { WRITEMASK = 0xf | REGID = r1.x } !+ 00000081 VFD_DEST_CNTL[0x2].INSTR: { WRITEMASK = 0x1 | REGID = r2.x } -!+ 80100180 SP_VS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 3 | BRANCHSTACK = 0 | THREADSIZE = THREAD128 | MERGEDREGS } -!+ 00000002 SP_VS_PRIMITIVE_CNTL: { OUT = 2 } +!+ 80100180 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 3 | BRANCHSTACK = 0 | THREADSIZE = THREAD128 | MERGEDREGS } +!+ 00000002 SP_VS_PRIMITIVE_CNTL: { OUT = 2 | FLAGS_REGID = r0.x } !+ 0f000f08 SP_VS_OUT[0].REG: { A_REGID = r2.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0xf } !+ 00000400 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 4 | OUTLOC2 = 0 | OUTLOC3 = 0 } !+ 01054000 SP_VS_OBJ_START: 0x1054000 base=1054000, offset=0, size=12288 @@ -1480,7 +1480,7 @@ t7 opcode: CP_DRAW_INDIRECT_MULTI (2a) (12 dwords) + 00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } + 00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } + 00000000 SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } -!+ 81500100 SP_FS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | BRANCHSTACK = 0 | THREADSIZE = THREAD128 | VARYING | MERGEDREGS | 0x1000000 } +!+ 81500100 SP_FS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | BRANCHSTACK = 0 | THREADSIZE = THREAD128 | VARYING | UNK24 | MERGEDREGS } !+ 01054080 SP_FS_OBJ_START: 0x1054080 base=1054000, offset=128, size=12288 0000000001054080: 0000: 00002000 47300002 00002001 47300003 00002002 47300004 00002003 47308005 00000000010540a0: 0020: 00000000 03000000 00000000 00000000 00000000 00000000 00000000 00000000 @@ -1516,7 +1516,7 @@ t7 opcode: CP_DRAW_INDIRECT_MULTI (2a) (12 dwords) !+ 000000fc SP_FS_OUTPUT[0x6].REG: { REGID = r63.x } !+ 000000fc SP_FS_OUTPUT[0x7].REG: { REGID = r63.x } !+ 00000030 SP_FS_MRT[0].REG: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM } -!+ 00007fc0 SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK4 = r63.x | 0x7000 } +!+ 00007fc0 SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK4 = r63.x | UNK12 = 0x7 } + 00000000 SP_CS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } !+ 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } !+ 00000001 SP_FS_INSTRLEN: 1 @@ -1532,7 +1532,7 @@ t7 opcode: CP_DRAW_INDIRECT_MULTI (2a) (12 dwords) !+ fcfcfcfc HLSQ_CONTROL_2_REG: { FACEREGID = r63.x | SAMPLEID = r63.x | SAMPLEMASK = r63.x | SIZE = r63.x } !+ fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ fcfcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | XYCOORDREGID = r63.x | ZWCOORDREGID = r63.x } - + 000000fc HLSQ_CONTROL_5_REG: 0xfc + + 000000fc HLSQ_CONTROL_5_REG: { UNK0 = r63.x } + 00000000 HLSQ_CS_CNTL: { CONSTLEN = 0 } !+ 0000009f HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | GFX_IBO | CS_BINDLESS = 0 | GFX_BINDLESS = 0 } !+ 00000100 HLSQ_FS_CNTL: { CONSTLEN = 0 | ENABLED } diff --git a/src/freedreno/.gitlab-ci/reference/fd-clouds.log b/src/freedreno/.gitlab-ci/reference/fd-clouds.log index 3cb2485c19d..c71f3f232e5 100644 --- a/src/freedreno/.gitlab-ci/reference/fd-clouds.log +++ b/src/freedreno/.gitlab-ci/reference/fd-clouds.log @@ -24,11 +24,11 @@ t4 write SP_UNKNOWN_AE00 (ae00) t4 write SP_PERFCTR_ENABLE (ae0f) SP_PERFCTR_ENABLE: { VS | HS | DS | GS | FS | CS } 0000000001d9102c: 0000: 40ae0f01 0000003f -t4 write SP_UNKNOWN_B605 (b605) - SP_UNKNOWN_B605: 0x44 +t4 write TPL1_UNKNOWN_B605 (b605) + TPL1_UNKNOWN_B605: 68 0000000001d91034: 0000: 40b60501 00000044 -t4 write SP_UNKNOWN_B600 (b600) - SP_UNKNOWN_B600: 0x100000 +t4 write TPL1_UNKNOWN_B600 (b600) + TPL1_UNKNOWN_B600: 0x100000 0000000001d9103c: 0000: 40b60001 00100000 t4 write HLSQ_UNKNOWN_BE00 (be00) HLSQ_UNKNOWN_BE00: 0x80 @@ -67,7 +67,7 @@ t4 write RB_UNKNOWN_8E01 (8e01) RB_UNKNOWN_8E01: 0x1 0000000001d9109c: 0000: 408e0101 00000001 t4 write SP_MODE_CONTROL (ab00) - SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | 0x4 } + SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | UNK2 } 0000000001d910a4: 0000: 40ab0001 00000005 t4 write VFD_ADD_OFFSET (a009) VFD_ADD_OFFSET: { VERTEX } @@ -175,7 +175,7 @@ t4 write SP_TP_SAMPLE_CONFIG (b304) SP_TP_SAMPLE_CONFIG: { 0 } 0000000001d911bc: 0000: 48b30401 00000000 t4 write SP_TP_UNKNOWN_B309 (b309) - SP_TP_UNKNOWN_B309: 0xa2 + SP_TP_UNKNOWN_B309: 162 0000000001d911c4: 0000: 40b30901 000000a2 t4 write RB_SAMPLE_CONFIG (8804) RB_SAMPLE_CONFIG: { 0 } @@ -202,7 +202,7 @@ t4 write RB_Z_BOUNDS_MAX (8879) RB_Z_BOUNDS_MAX: 0.000000 0000000001d91204: 0000: 40887901 00000000 t4 write HLSQ_CONTROL_5_REG (b986) - HLSQ_CONTROL_5_REG: 0xfc + HLSQ_CONTROL_5_REG: { UNK0 = r63.x } 0000000001d9120c: 0000: 48b98601 000000fc t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) 0000000001d91214: 0000: 70268000 @@ -607,19 +607,19 @@ t4 write SP_HS_OBJ_FIRST_EXEC_OFFSET (a833) SP_HS_OBJ_FIRST_EXEC_OFFSET: 0 0000000001121000: 0000: 40a83301 00000000 t4 write SP_FS_PREFETCH_CNTL (a99e) - SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK4 = r63.x | 0x7000 } + SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK4 = r63.x | UNK12 = 0x7 } 0000000001121008: 0000: 40a99e01 00007fc0 t4 write SP_UNKNOWN_A9A8 (a9a8) SP_UNKNOWN_A9A8: 0 0000000001121010: 0000: 40a9a801 00000000 t4 write SP_MODE_CONTROL (ab00) - SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | 0x4 } + SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | UNK2 } 0000000001121018: 0000: 40ab0001 00000005 t4 write SP_FS_OUTPUT_CNTL0 (a98c) SP_FS_OUTPUT_CNTL0: { DEPTH_REGID = r63.x | SAMPMASK_REGID = r63.x | STENCILREF_REGID = r63.x } 0000000001121020: 0000: 40a98c01 fcfcfc00 t4 write SP_VS_CTRL_REG0 (a800) - SP_VS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | BRANCHSTACK = 0 | THREADSIZE = THREAD128 | MERGEDREGS } + SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | BRANCHSTACK = 0 | THREADSIZE = THREAD128 | MERGEDREGS } 0000000001121028: 0000: 40a80001 80100080 t4 write SP_VS_INSTRLEN (a824) SP_VS_INSTRLEN: 1 @@ -671,7 +671,7 @@ t4 write SP_HS_WAVE_INPUT_SIZE (a831) SP_HS_WAVE_INPUT_SIZE: 0 0000000001121078: 0000: 48a83101 00000000 t4 write SP_VS_PRIMITIVE_CNTL (a802) - SP_VS_PRIMITIVE_CNTL: { OUT = 1 } + SP_VS_PRIMITIVE_CNTL: { OUT = 1 | FLAGS_REGID = r0.x } 0000000001121080: 0000: 48a80201 00000001 t4 write VPC_CNTL_0 (9304) VPC_CNTL_0: { NUMNONPOSVAR = 0 | PRIMIDLOC = 255 | VIEWIDLOC = 255 } @@ -687,13 +687,13 @@ t4 write HLSQ_CONTROL_1_REG (b982) HLSQ_CONTROL_2_REG: { FACEREGID = r63.x | SAMPLEID = r63.x | SAMPLEMASK = r63.x | SIZE = r63.x } HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | XYCOORDREGID = r63.x | ZWCOORDREGID = r63.x } - HLSQ_CONTROL_5_REG: 0xfc + HLSQ_CONTROL_5_REG: { UNK0 = r63.x } 00000000011210a0: 0000: 40b98285 00000007 fcfcfcfc fcfcfcfc fcfcfcfc 000000fc t4 write HLSQ_FS_CNTL_0 (b980) HLSQ_FS_CNTL_0: { THREADSIZE = THREAD128 } 00000000011210b8: 0000: 48b98001 00000001 t4 write SP_FS_CTRL_REG0 (a980) - SP_FS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | BRANCHSTACK = 0 | THREADSIZE = THREAD128 | MERGEDREGS | 0x1000000 } + SP_FS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | BRANCHSTACK = 0 | THREADSIZE = THREAD128 | UNK24 | MERGEDREGS } 00000000011210c0: 0000: 40a98001 81100080 t4 write SP_FS_OBJ_FIRST_EXEC_OFFSET (a982) SP_FS_OBJ_FIRST_EXEC_OFFSET: 0 @@ -746,9 +746,9 @@ t4 write VPC_UNKNOWN_9107 (9107) t4 write VFD_CONTROL_1 (a001) VFD_CONTROL_1: { REGID4VTX = r63.x | REGID4INST = r63.x | REGID4PRIMID = r63.x | REGID4VIEWID = r63.x } VFD_CONTROL_2: { REGID_HSPATCHID = r63.x | REGID_INVOCATIONID = r63.x } - VFD_CONTROL_3: { REGID_DSPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x | 0xfc } - VFD_CONTROL_4: 0xfc - VFD_CONTROL_5: { REGID_GSHEADER = r63.x | 0xfc00 } + VFD_CONTROL_3: { UNK0 = r63.x | REGID_DSPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + VFD_CONTROL_4: { UNK0 = r63.x } + VFD_CONTROL_5: { REGID_GSHEADER = r63.x | UNK8 = r63.x } VFD_CONTROL_6: { 0 } 0000000001121150: 0000: 40a00186 fcfcfcfc 0000fcfc fcfcfcfc 000000fc 0000fcfc 00000000 t4 write RB_DEPTH_PLANE_CNTL (8870) @@ -786,7 +786,7 @@ t4 write VFD_FETCH[0].BASE (a010) 0000000001116000: 0000: 40a01004 01016000 00000000 00100000 0000000c t4 write VFD_DECODE[0].INSTR (a090) VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = FMT6_32_32_32_FLOAT | SWAP = WZYX | UNK30 | FLOAT } - VFD_DECODE[0].STEP_RATE: 0x1 + VFD_DECODE[0].STEP_RATE: 1 0000000001116014: 0000: 48a09002 c7400000 00000001 t4 write VFD_DEST_CNTL[0].INSTR (a0d0) VFD_DEST_CNTL[0].INSTR: { WRITEMASK = 0xf | REGID = r0.x } @@ -1059,9 +1059,9 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) !+ 00000101 VFD_CONTROL_0: { FETCH_CNT = 1 | DECODE_CNT = 1 } !+ fcfcfcfc VFD_CONTROL_1: { REGID4VTX = r63.x | REGID4INST = r63.x | REGID4PRIMID = r63.x | REGID4VIEWID = r63.x } !+ 0000fcfc VFD_CONTROL_2: { REGID_HSPATCHID = r63.x | REGID_INVOCATIONID = r63.x } -!+ fcfcfcfc VFD_CONTROL_3: { REGID_DSPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x | 0xfc } -!+ 000000fc VFD_CONTROL_4: 0xfc -!+ 0000fcfc VFD_CONTROL_5: { REGID_GSHEADER = r63.x | 0xfc00 } +!+ fcfcfcfc VFD_CONTROL_3: { UNK0 = r63.x | REGID_DSPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } +!+ 000000fc VFD_CONTROL_4: { UNK0 = r63.x } +!+ 0000fcfc VFD_CONTROL_5: { REGID_GSHEADER = r63.x | UNK8 = r63.x } + 00000000 VFD_CONTROL_6: { 0 } !+ 00000001 VFD_MODE_CNTL: { BINNING_PASS } + 00000000 VFD_MULTIVIEW_CNTL: { VIEWS = 0 } @@ -1073,11 +1073,11 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) !+ 00100000 VFD_FETCH[0].SIZE: 1048576 !+ 0000000c VFD_FETCH[0].STRIDE: 12 !+ c7400000 VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = FMT6_32_32_32_FLOAT | SWAP = WZYX | UNK30 | FLOAT } -!+ 00000001 VFD_DECODE[0].STEP_RATE: 0x1 +!+ 00000001 VFD_DECODE[0].STEP_RATE: 1 !+ 0000000f VFD_DEST_CNTL[0].INSTR: { WRITEMASK = 0xf | REGID = r0.x } !+ 00000001 SP_UNKNOWN_A0F8: 0x1 -!+ 80100080 SP_VS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | BRANCHSTACK = 0 | THREADSIZE = THREAD128 | MERGEDREGS } -!+ 00000001 SP_VS_PRIMITIVE_CNTL: { OUT = 1 } +!+ 80100080 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | BRANCHSTACK = 0 | THREADSIZE = THREAD128 | MERGEDREGS } +!+ 00000001 SP_VS_PRIMITIVE_CNTL: { OUT = 1 | FLAGS_REGID = r0.x } !+ 00000f00 SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_FIRST_EXEC_OFFSET: 0 @@ -1103,7 +1103,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) + 00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } + 00000000 SP_GS_PRIM_SIZE: 0 + 00000000 SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } -!+ 81100080 SP_FS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | BRANCHSTACK = 0 | THREADSIZE = THREAD128 | MERGEDREGS | 0x1000000 } +!+ 81100080 SP_FS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | BRANCHSTACK = 0 | THREADSIZE = THREAD128 | UNK24 | MERGEDREGS } + 00000000 SP_FS_OBJ_FIRST_EXEC_OFFSET: 0 + 00000000 SP_SRGB_CNTL: { 0 } !+ 0000000f SP_FS_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } @@ -1117,9 +1117,9 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) !+ 000000fc SP_FS_OUTPUT[0x6].REG: { REGID = r63.x } !+ 000000fc SP_FS_OUTPUT[0x7].REG: { REGID = r63.x } !+ 00000031 SP_FS_MRT[0].REG: { COLOR_FORMAT = FMT6_8_8_8_X8_UNORM } -!+ 00007fc0 SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK4 = r63.x | 0x7000 } +!+ 00007fc0 SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK4 = r63.x | UNK12 = 0x7 } + 00000000 SP_UNKNOWN_A9A8: 0 -!+ 00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | 0x4 } +!+ 00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | UNK2 } !+ 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } + 00000000 SP_IBO_COUNT: 0 + 00000000 SP_UNKNOWN_AE00: 0 @@ -1132,9 +1132,9 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) !+ 00000004 SP_TP_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE } + 00000000 SP_TP_SAMPLE_CONFIG: { 0 } + 00000000 SP_TP_WINDOW_OFFSET: { X = 0 | Y = 0 } -!+ 000000a2 SP_TP_UNKNOWN_B309: 0xa2 -!+ 00100000 SP_UNKNOWN_B600: 0x100000 -!+ 00000044 SP_UNKNOWN_B605: 0x44 +!+ 000000a2 SP_TP_UNKNOWN_B309: 162 +!+ 00100000 TPL1_UNKNOWN_B600: 0x100000 +!+ 00000044 TPL1_UNKNOWN_B605: 68 !+ 00000100 HLSQ_VS_CNTL: { CONSTLEN = 0 | ENABLED } + 00000000 HLSQ_HS_CNTL: { CONSTLEN = 0 } + 00000000 HLSQ_DS_CNTL: { CONSTLEN = 0 } @@ -1144,7 +1144,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) !+ fcfcfcfc HLSQ_CONTROL_2_REG: { FACEREGID = r63.x | SAMPLEID = r63.x | SAMPLEMASK = r63.x | SIZE = r63.x } !+ fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ fcfcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | XYCOORDREGID = r63.x | ZWCOORDREGID = r63.x } -!+ 000000fc HLSQ_CONTROL_5_REG: 0xfc +!+ 000000fc HLSQ_CONTROL_5_REG: { UNK0 = r63.x } !+ 000000ff HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_IBO | GFX_IBO | CS_BINDLESS = 0 | GFX_BINDLESS = 0 } !+ 00000108 HLSQ_FS_CNTL: { CONSTLEN = 32 | ENABLED } + 00000000 HLSQ_SHARED_CONSTS: { 0 } @@ -1901,19 +1901,19 @@ t4 write SP_HS_OBJ_FIRST_EXEC_OFFSET (a833) SP_HS_OBJ_FIRST_EXEC_OFFSET: 0 0000000001120000: 0000: 40a83301 00000000 t4 write SP_FS_PREFETCH_CNTL (a99e) - SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK4 = r63.x | 0x7000 } + SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK4 = r63.x | UNK12 = 0x7 } 0000000001120008: 0000: 40a99e01 00007fc0 t4 write SP_UNKNOWN_A9A8 (a9a8) SP_UNKNOWN_A9A8: 0 0000000001120010: 0000: 40a9a801 00000000 t4 write SP_MODE_CONTROL (ab00) - SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | 0x4 } + SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | UNK2 } 0000000001120018: 0000: 40ab0001 00000005 t4 write SP_FS_OUTPUT_CNTL0 (a98c) SP_FS_OUTPUT_CNTL0: { DEPTH_REGID = r63.x | SAMPMASK_REGID = r63.x | STENCILREF_REGID = r63.x } 0000000001120020: 0000: 40a98c01 fcfcfc00 t4 write SP_VS_CTRL_REG0 (a800) - SP_VS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | BRANCHSTACK = 0 | THREADSIZE = THREAD128 | MERGEDREGS } + SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | BRANCHSTACK = 0 | THREADSIZE = THREAD128 | MERGEDREGS } 0000000001120028: 0000: 40a80001 80100080 t4 write SP_VS_INSTRLEN (a824) SP_VS_INSTRLEN: 1 @@ -1965,7 +1965,7 @@ t4 write SP_HS_WAVE_INPUT_SIZE (a831) SP_HS_WAVE_INPUT_SIZE: 0 0000000001120078: 0000: 48a83101 00000000 t4 write SP_VS_PRIMITIVE_CNTL (a802) - SP_VS_PRIMITIVE_CNTL: { OUT = 1 } + SP_VS_PRIMITIVE_CNTL: { OUT = 1 | FLAGS_REGID = r0.x } 0000000001120080: 0000: 48a80201 00000001 t4 write VPC_CNTL_0 (9304) VPC_CNTL_0: { NUMNONPOSVAR = 0 | PRIMIDLOC = 255 | VIEWIDLOC = 255 } @@ -1981,13 +1981,13 @@ t4 write HLSQ_CONTROL_1_REG (b982) HLSQ_CONTROL_2_REG: { FACEREGID = r63.x | SAMPLEID = r63.x | SAMPLEMASK = r63.x | SIZE = r63.x } HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | XYCOORDREGID = r4.w | ZWCOORDREGID = r5.y } - HLSQ_CONTROL_5_REG: 0xfc + HLSQ_CONTROL_5_REG: { UNK0 = r63.x } 00000000011200a0: 0000: 40b98285 00000007 fcfcfcfc fcfcfcfc 1513fcfc 000000fc t4 write HLSQ_FS_CNTL_0 (b980) HLSQ_FS_CNTL_0: { THREADSIZE = THREAD128 } 00000000011200b8: 0000: 48b98001 00000001 t4 write SP_FS_CTRL_REG0 (a980) - SP_FS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 19 | BRANCHSTACK = 2 | THREADSIZE = THREAD128 | VARYING | MERGEDREGS | 0x1000000 } + SP_FS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 19 | BRANCHSTACK = 2 | THREADSIZE = THREAD128 | VARYING | UNK24 | MERGEDREGS } 00000000011200c0: 0000: 40a98001 81508980 t4 write SP_FS_OBJ_FIRST_EXEC_OFFSET (a982) SP_FS_OBJ_FIRST_EXEC_OFFSET: 0 @@ -4888,9 +4888,9 @@ t7 opcode: CP_LOAD_STATE6_FRAG (34) (4 dwords) t4 write VFD_CONTROL_1 (a001) VFD_CONTROL_1: { REGID4VTX = r63.x | REGID4INST = r63.x | REGID4PRIMID = r63.x | REGID4VIEWID = r63.x } VFD_CONTROL_2: { REGID_HSPATCHID = r63.x | REGID_INVOCATIONID = r63.x } - VFD_CONTROL_3: { REGID_DSPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x | 0xfc } - VFD_CONTROL_4: 0xfc - VFD_CONTROL_5: { REGID_GSHEADER = r63.x | 0xfc00 } + VFD_CONTROL_3: { UNK0 = r63.x | REGID_DSPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + VFD_CONTROL_4: { UNK0 = r63.x } + VFD_CONTROL_5: { REGID_GSHEADER = r63.x | UNK8 = r63.x } VFD_CONTROL_6: { 0 } 0000000001120174: 0000: 40a00186 fcfcfcfc 0000fcfc fcfcfcfc 000000fc 0000fcfc 00000000 t4 write RB_DEPTH_PLANE_CNTL (8870) @@ -5001,7 +5001,7 @@ t4 write VFD_FETCH[0].BASE (a010) 0000000001116000: 0000: 40a01004 01016000 00000000 00100000 0000000c t4 write VFD_DECODE[0].INSTR (a090) VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = FMT6_32_32_32_FLOAT | SWAP = WZYX | UNK30 | FLOAT } - VFD_DECODE[0].STEP_RATE: 0x1 + VFD_DECODE[0].STEP_RATE: 1 0000000001116014: 0000: 48a09002 c7400000 00000001 t4 write VFD_DEST_CNTL[0].INSTR (a0d0) VFD_DEST_CNTL[0].INSTR: { WRITEMASK = 0xf | REGID = r0.x } @@ -5260,9 +5260,9 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) + 00000101 VFD_CONTROL_0: { FETCH_CNT = 1 | DECODE_CNT = 1 } + fcfcfcfc VFD_CONTROL_1: { REGID4VTX = r63.x | REGID4INST = r63.x | REGID4PRIMID = r63.x | REGID4VIEWID = r63.x } + 0000fcfc VFD_CONTROL_2: { REGID_HSPATCHID = r63.x | REGID_INVOCATIONID = r63.x } - + fcfcfcfc VFD_CONTROL_3: { REGID_DSPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x | 0xfc } - + 000000fc VFD_CONTROL_4: 0xfc - + 0000fcfc VFD_CONTROL_5: { REGID_GSHEADER = r63.x | 0xfc00 } + + fcfcfcfc VFD_CONTROL_3: { UNK0 = r63.x | REGID_DSPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + + 000000fc VFD_CONTROL_4: { UNK0 = r63.x } + + 0000fcfc VFD_CONTROL_5: { REGID_GSHEADER = r63.x | UNK8 = r63.x } + 00000000 VFD_CONTROL_6: { 0 } + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 VFD_INSTANCE_START_OFFSET: 0 @@ -5271,10 +5271,10 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) + 00100000 VFD_FETCH[0].SIZE: 1048576 + 0000000c VFD_FETCH[0].STRIDE: 12 + c7400000 VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = FMT6_32_32_32_FLOAT | SWAP = WZYX | UNK30 | FLOAT } - + 00000001 VFD_DECODE[0].STEP_RATE: 0x1 + + 00000001 VFD_DECODE[0].STEP_RATE: 1 + 0000000f VFD_DEST_CNTL[0].INSTR: { WRITEMASK = 0xf | REGID = r0.x } - + 80100080 SP_VS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | BRANCHSTACK = 0 | THREADSIZE = THREAD128 | MERGEDREGS } - + 00000001 SP_VS_PRIMITIVE_CNTL: { OUT = 1 } + + 80100080 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | BRANCHSTACK = 0 | THREADSIZE = THREAD128 | MERGEDREGS } + + 00000001 SP_VS_PRIMITIVE_CNTL: { OUT = 1 | FLAGS_REGID = r0.x } + 00000f00 SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } !+ 01012000 SP_VS_OBJ_START: 0x1012000 base=1012000, offset=0, size=128 @@ -5299,7 +5299,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) + 00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } + 00000000 SP_GS_PRIM_SIZE: 0 + 00000000 SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } -!+ 81508980 SP_FS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 19 | BRANCHSTACK = 2 | THREADSIZE = THREAD128 | VARYING | MERGEDREGS | 0x1000000 } +!+ 81508980 SP_FS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 19 | BRANCHSTACK = 2 | THREADSIZE = THREAD128 | VARYING | UNK24 | MERGEDREGS } + 00000000 SP_FS_OBJ_FIRST_EXEC_OFFSET: 0 !+ 01013000 SP_FS_OBJ_START: 0x1013000 base=1013000, offset=0, size=11264 0000000001013000: 0000: 40400000 204cc000 00000000 204cc006 3e99999a 204cc004 20080014 42700008 @@ -6736,9 +6736,9 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) !+ 00000004 SP_FS_OUTPUT[0x5].REG: { REGID = r1.x } !+ 00000004 SP_FS_OUTPUT[0x6].REG: { REGID = r1.x } !+ 00000004 SP_FS_OUTPUT[0x7].REG: { REGID = r1.x } - + 00007fc0 SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK4 = r63.x | 0x7000 } + + 00007fc0 SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK4 = r63.x | UNK12 = 0x7 } + 00000000 SP_UNKNOWN_A9A8: 0 - + 00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | 0x4 } + + 00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | UNK2 } + 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } !+ 00000058 SP_FS_INSTRLEN: 88 !+ 011160a0 SP_IBO: 0x11160a0 base=1116000, offset=160, size=388 @@ -6753,7 +6753,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) + fcfcfcfc HLSQ_CONTROL_2_REG: { FACEREGID = r63.x | SAMPLEID = r63.x | SAMPLEMASK = r63.x | SIZE = r63.x } + fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 1513fcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | XYCOORDREGID = r4.w | ZWCOORDREGID = r5.y } - + 000000fc HLSQ_CONTROL_5_REG: 0xfc + + 000000fc HLSQ_CONTROL_5_REG: { UNK0 = r63.x } + 000000ff HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_IBO | GFX_IBO | CS_BINDLESS = 0 | GFX_BINDLESS = 0 } + 00000108 HLSQ_FS_CNTL: { CONSTLEN = 32 | ENABLED } 0000000001d8f130: 0000: 70388003 00000186 00000001 00000004 diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml index f03d22a34de..6a50378ad2b 100644 --- a/src/freedreno/registers/adreno/a6xx.xml +++ b/src/freedreno/registers/adreno/a6xx.xml @@ -1358,10 +1358,8 @@ to upconvert to 32b float internally? - - @@ -1380,15 +1378,6 @@ to upconvert to 32b float internally? - - - - - - - - - @@ -1453,11 +1442,6 @@ to upconvert to 32b float internally? - - - - - @@ -2199,9 +2183,14 @@ to upconvert to 32b float internally? + + + + + @@ -2618,14 +2607,17 @@ to upconvert to 32b float internally? + + + - + + + + + + + + + + - + + + + + @@ -2732,20 +2745,22 @@ to upconvert to 32b float internally? --> - + + + + + + + + - - - - - - - + + + + @@ -2835,9 +2850,9 @@ to upconvert to 32b float internally? - + - + @@ -2848,22 +2863,24 @@ to upconvert to 32b float internally? 64 (wavesize) * 64 (SP_HS_WAVE_INPUT_SIZE) * 4 = 16k --> + + - + - + - - - - + + + + @@ -2881,33 +2898,23 @@ to upconvert to 32b float internally? + - + - + - - - - - - - - - - - - + + + + @@ -2926,14 +2933,15 @@ to upconvert to 32b float internally? + - + - + @@ -2945,14 +2953,10 @@ to upconvert to 32b float internally? - - - - + + + @@ -2996,11 +3000,20 @@ to upconvert to 32b float internally? + + per MRT + + + + + + + @@ -3010,6 +3023,7 @@ to upconvert to 32b float internally? + @@ -3029,24 +3043,24 @@ to upconvert to 32b float internally? - - - - + + - - - - - - + + + + + + + + - + bit 0 seems to toggle between 2k and 32k of shared storage the ldl/stl offset seems to be rewritten to 0 when it is beyond @@ -3054,31 +3068,18 @@ to upconvert to 32b float internally? 64k (and has 36k of storage on A640 - reads between 36k-64k always return 0) - + + - - - - - - - - - per MRT - - - - - - - + + - + This seems to be be the equivalent of HWSTACKOFFSET in @@ -3089,17 +3090,24 @@ to upconvert to 32b float internally? + + + + + + + + - + - + + + - + - + + - + @@ -3139,11 +3151,14 @@ to upconvert to 32b float internally? - - + + + + - + + + - - - + + + + + + @@ -3182,8 +3202,8 @@ to upconvert to 32b float internally? - - + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - + + + + + + + + @@ -3224,17 +3267,19 @@ to upconvert to 32b float internally? - + - + + + - - + + @@ -3262,10 +3307,12 @@ to upconvert to 32b float internally? - + + + @@ -3292,26 +3339,38 @@ to upconvert to 32b float internally? + + - + + + + + + - + + @@ -3382,7 +3441,8 @@ to upconvert to 32b float internally? - + + @@ -3390,14 +3450,15 @@ to upconvert to 32b float internally? - - - - - + + + + + +