i965: Re-emit l3 state before BLORP executes

If BLORP is the first thing to execute, we may not have set the L3$
config yet.  That's not normally a problem but we're about to add code
to BLORP which will look at brw_context::l3::config and we'd like that
to be initialized.  It's also just good practice.

Cc: "20.0" mesa-stable@lists.freedesktop.org
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
(cherry picked from commit 9d05822cb8)

.pick_status.json

@@ -193,7 +193,7 @@
         "description": "i965: Re-emit l3 state before BLORP executes",
         "nominated": true,
         "nomination_type": 0,
-        "resolution": 0,
+        "resolution": 1,
         "master_sha": null,
         "because_sha": null
     },

src/mesa/drivers/dri/i965/brw_context.h

@@ -1504,6 +1504,9 @@ gen6_set_sample_maps(struct gl_context *ctx);
 /* gen8_multisample_state.c */
 void gen8_emit_3dstate_sample_pattern(struct brw_context *brw);
 
+/* gen7_l3_state.c */
+void brw_emit_l3_state(struct brw_context *brw);
+
 /* gen7_urb.c */
 void
 gen7_emit_push_constant_state(struct brw_context *brw, unsigned vs_size,

src/mesa/drivers/dri/i965/gen7_l3_state.c

@@ -212,8 +212,8 @@ update_urb_size(struct brw_context *brw, const struct gen_l3_config *cfg)
    }
 }
 
-static void
-emit_l3_state(struct brw_context *brw)
+void
+brw_emit_l3_state(struct brw_context *brw)
 {
    const struct gen_l3_weights w = get_pipeline_state_l3_weights(brw);
    const float dw = gen_diff_l3_weights(w, gen_get_l3_config_weights(brw->l3.config));
@@ -261,7 +261,7 @@ const struct brw_tracked_state gen7_l3_state = {
              BRW_NEW_TES_PROG_DATA |
              BRW_NEW_VS_PROG_DATA,
    },
-   .emit = emit_l3_state
+   .emit = brw_emit_l3_state
 };
 
 /**

src/mesa/drivers/dri/i965/genX_blorp_exec.c

@@ -317,6 +317,7 @@ genX(blorp_exec)(struct blorp_batch *batch,
       brw_cache_flush_for_depth(brw, params->stencil.addr.buffer);
 
    brw_select_pipeline(brw, BRW_RENDER_PIPELINE);
+   brw_emit_l3_state(brw);
 
 retry:
    intel_batchbuffer_require_space(brw, 1400);