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winsys/amdgpu: add DOORBELL domain to bo

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Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29010>
This commit is contained in:
Yogesh Mohan Marimuthu 2024-08-02 11:24:02 +05:30 • committed by Marge Bot
parent 42d49faee5
commit 468ea03c6e
2 changed files with 12 additions and 3 deletions
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5
src/gallium/include/winsys/radeon_winsys.h
View file

@ -45,6 +45,7 @@ enum radeon_bo_domain
RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT,
RADEON_DOMAIN_GDS = 8,
RADEON_DOMAIN_OA = 16,
RADEON_DOMAIN_DOORBELL = 32,
};
enum radeon_bo_flag
@ -891,6 +892,10 @@ static void radeon_canonicalize_bo_flags(enum radeon_bo_domain *_domain,
flags |= RADEON_FLAG_NO_SUBALLOC | RADEON_FLAG_NO_CPU_ACCESS;
flags &= ~RADEON_FLAG_SPARSE;
break;
case RADEON_DOMAIN_DOORBELL:
flags |= RADEON_FLAG_NO_SUBALLOC;
flags &= ~RADEON_FLAG_SPARSE;
break;
}
/* Sparse buffers must have NO_CPU_ACCESS set. */

10
src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
View file

@ -484,7 +484,8 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct amdgpu_winsys *aws,
/* VRAM or GTT must be specified, but not both at the same time. */
assert(util_bitcount(initial_domain & (RADEON_DOMAIN_VRAM_GTT |
RADEON_DOMAIN_GDS |
RADEON_DOMAIN_OA)) == 1);
RADEON_DOMAIN_OA |
RADEON_DOMAIN_DOORBELL)) == 1);
alignment = amdgpu_get_optimal_alignment(aws, size, alignment);
@ -532,6 +533,8 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct amdgpu_winsys *aws,
request.preferred_heap |= AMDGPU_GEM_DOMAIN_GDS;
if (initial_domain & RADEON_DOMAIN_OA)
request.preferred_heap |= AMDGPU_GEM_DOMAIN_OA;
if (initial_domain & RADEON_DOMAIN_DOORBELL)
request.preferred_heap |= AMDGPU_GEM_DOMAIN_DOORBELL;
if (flags & RADEON_FLAG_NO_CPU_ACCESS)
request.flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
@ -1435,8 +1438,9 @@ no_slab:
alignment = align(alignment, aws->info.gart_page_size);
}
bool use_reusable_pool = flags & RADEON_FLAG_NO_INTERPROCESS_SHARING &&
!(flags & RADEON_FLAG_DISCARDABLE);
bool use_reusable_pool = !(domain & RADEON_DOMAIN_DOORBELL) &&
(flags & RADEON_FLAG_NO_INTERPROCESS_SHARING) &&
!(flags & RADEON_FLAG_DISCARDABLE);
if (use_reusable_pool) {
/* RADEON_FLAG_NO_SUBALLOC is irrelevant for the cache. */