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radeonsi/gfx11: move the PIXEL_PIPE_STAT_CONTROL event into the GFX preambles

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Both the normal and shadowing preamable should do this.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>
This commit is contained in:
Marek Olšák 2023-01-24 06:02:15 -05:00 • committed by Marge Bot
parent 383269238d
commit 4664b22f65
3 changed files with 18 additions and 11 deletions
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9
src/amd/common/ac_shadowed_regs.c
View file

@ -4196,6 +4196,15 @@ void ac_create_shadowing_ib_preamble(const struct radeon_info *info,
pm4_cmd_add(pm4_cmdbuf, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
if (info->gfx_level >= GFX11) {
uint64_t rb_mask = BITFIELD64_MASK(info->max_render_backends);
pm4_cmd_add(pm4_cmdbuf, PKT3(PKT3_EVENT_WRITE, 2, 0));
pm4_cmd_add(pm4_cmdbuf, EVENT_TYPE(V_028A90_PIXEL_PIPE_STAT_CONTROL) | EVENT_INDEX(1));
pm4_cmd_add(pm4_cmdbuf, PIXEL_PIPE_STATE_CNTL_COUNTER_ID(0) |
PIXEL_PIPE_STATE_CNTL_STRIDE(2) |
PIXEL_PIPE_STATE_CNTL_INSTANCE_EN_LO(rb_mask));
pm4_cmd_add(pm4_cmdbuf, PIXEL_PIPE_STATE_CNTL_INSTANCE_EN_HI(rb_mask));
/* We must wait for idle using an EOP event before changing the attribute ring registers.
* Use the bottom-of-pipe EOP event, but increment the PWS counter instead of writing memory.
*/

11
src/gallium/drivers/radeonsi/si_query.c
View file

@ -813,17 +813,6 @@ static void si_query_hw_do_emit_start(struct si_context *sctx, struct si_query_h
case PIPE_QUERY_OCCLUSION_PREDICATE:
case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE: {
radeon_begin(cs);
if (sctx->gfx_level >= GFX11) {
uint64_t rb_mask = BITFIELD64_MASK(sctx->screen->info.max_render_backends);
radeon_emit(PKT3(PKT3_EVENT_WRITE, 2, 0));
radeon_emit(EVENT_TYPE(V_028A90_PIXEL_PIPE_STAT_CONTROL) | EVENT_INDEX(1));
radeon_emit(PIXEL_PIPE_STATE_CNTL_COUNTER_ID(0) |
PIXEL_PIPE_STATE_CNTL_STRIDE(2) |
PIXEL_PIPE_STATE_CNTL_INSTANCE_EN_LO(rb_mask));
radeon_emit(PIXEL_PIPE_STATE_CNTL_INSTANCE_EN_HI(rb_mask));
}
radeon_emit(PKT3(PKT3_EVENT_WRITE, 2, 0));
if (sctx->gfx_level >= GFX11)
radeon_emit(EVENT_TYPE(V_028A90_PIXEL_PIPE_STAT_DUMP) | EVENT_INDEX(1));

9
src/gallium/drivers/radeonsi/si_state.c
View file

@ -5920,6 +5920,15 @@ void si_init_cs_preamble_state(struct si_context *sctx, bool uses_reg_shadowing)
si_pm4_set_reg(pm4, R_028620_PA_RATE_CNTL,
S_028620_VERTEX_RATE(2) | S_028620_PRIM_RATE(1));
uint64_t rb_mask = BITFIELD64_MASK(sctx->screen->info.max_render_backends);
si_pm4_cmd_add(pm4, PKT3(PKT3_EVENT_WRITE, 2, 0));
si_pm4_cmd_add(pm4, EVENT_TYPE(V_028A90_PIXEL_PIPE_STAT_CONTROL) | EVENT_INDEX(1));
si_pm4_cmd_add(pm4, PIXEL_PIPE_STATE_CNTL_COUNTER_ID(0) |
PIXEL_PIPE_STATE_CNTL_STRIDE(2) |
PIXEL_PIPE_STATE_CNTL_INSTANCE_EN_LO(rb_mask));
si_pm4_cmd_add(pm4, PIXEL_PIPE_STATE_CNTL_INSTANCE_EN_HI(rb_mask));
/* We must wait for idle using an EOP event before changing the attribute ring registers.
* Use the bottom-of-pipe EOP event, but increment the PWS counter instead of writing memory.
*/