diff --git a/src/gallium/drivers/r600/sfn/sfn_nir.cpp b/src/gallium/drivers/r600/sfn/sfn_nir.cpp index 73ddfe7bc63..fc7c9909b66 100644 --- a/src/gallium/drivers/r600/sfn/sfn_nir.cpp +++ b/src/gallium/drivers/r600/sfn/sfn_nir.cpp @@ -825,51 +825,35 @@ int r600_shader_from_nir(struct r600_context *rctx, NIR_PASS_V(sel->nir, nir_lower_io, nir_var_uniform, r600_glsl_type_size, nir_lower_io_lower_64bit_to_32); - if (sel->nir->info.stage == MESA_SHADER_VERTEX) { + nir_variable_mode io_modes = (nir_variable_mode)0; + if (sel->nir->info.stage != MESA_SHADER_VERTEX) + io_modes = nir_var_shader_in; + + if (sel->nir->info.stage != MESA_SHADER_FRAGMENT) + io_modes |= nir_var_shader_out; + + NIR_PASS_V(sel->nir, nir_lower_io, io_modes, r600_glsl_type_size, + nir_lower_io_lower_64bit_to_32); + + NIR_PASS_V(sel->nir, nir_opt_constant_folding); + NIR_PASS_V(sel->nir, nir_io_add_const_offset_to_base, io_modes); + + if (sel->nir->info.stage == MESA_SHADER_VERTEX) NIR_PASS_V(sel->nir, r600_vectorize_vs_inputs); - NIR_PASS_V(sel->nir, nir_lower_io, nir_var_shader_out, r600_glsl_type_size, - nir_lower_io_lower_64bit_to_32); - if (key->vs.as_ls) - NIR_PASS_V(sel->nir, r600_lower_tess_io, (pipe_prim_type)key->tcs.prim_mode); - } if (sel->nir->info.stage == MESA_SHADER_FRAGMENT) { - NIR_PASS_V(sel->nir, nir_lower_io, nir_var_shader_in, r600_glsl_type_size, - (nir_lower_io_options) - (nir_lower_io_lower_64bit_to_32)); NIR_PASS_V(sel->nir, r600_lower_fs_pos_input); NIR_PASS_V(sel->nir, r600_lower_fs_out_to_vector); } - if (sel->nir->info.stage == MESA_SHADER_TESS_CTRL) { - NIR_PASS_V(sel->nir, nir_lower_io, nir_var_shader_out, r600_glsl_type_size, - nir_lower_io_lower_64bit_to_32); - NIR_PASS_V(sel->nir, r600_lower_tess_io, (pipe_prim_type)key->tcs.prim_mode); - } - - if (sel->nir->info.stage == MESA_SHADER_GEOMETRY) { - NIR_PASS_V(sel->nir, nir_lower_io, nir_var_shader_out, r600_glsl_type_size, - nir_lower_io_lower_64bit_to_32); - NIR_PASS_V(sel->nir, nir_lower_io, nir_var_shader_in, r600_glsl_type_size, - nir_lower_io_lower_64bit_to_32); - } - if (sel->nir->info.stage == MESA_SHADER_TESS_CTRL || - sel->nir->info.stage == MESA_SHADER_TESS_EVAL) { - NIR_PASS_V(sel->nir, nir_lower_io, nir_var_shader_in, r600_glsl_type_size, - nir_lower_io_lower_64bit_to_32); - NIR_PASS_V(sel->nir, nir_lower_io, nir_var_shader_out, r600_glsl_type_size, - nir_lower_io_lower_64bit_to_32); - } - - if (sel->nir->info.stage == MESA_SHADER_TESS_CTRL || - sel->nir->info.stage == MESA_SHADER_TESS_EVAL) { - auto prim_type = sel->nir->info.stage == MESA_SHADER_TESS_CTRL ? - key->tcs.prim_mode : sel->nir->info.tess.primitive_mode; + sel->nir->info.stage == MESA_SHADER_TESS_EVAL || + (sel->nir->info.stage == MESA_SHADER_VERTEX && key->vs.as_ls)) { + auto prim_type = sel->nir->info.stage == MESA_SHADER_TESS_EVAL ? + sel->nir->info.tess.primitive_mode: key->tcs.prim_mode; NIR_PASS_V(sel->nir, r600_lower_tess_io, static_cast(prim_type)); } - if (sel->nir->info.stage == MESA_SHADER_TESS_CTRL) NIR_PASS_V(sel->nir, r600_append_tcs_TF_emission, (pipe_prim_type)key->tcs.prim_mode); diff --git a/src/gallium/drivers/r600/sfn/sfn_nir_lower_tess_io.cpp b/src/gallium/drivers/r600/sfn/sfn_nir_lower_tess_io.cpp index 21015e0434d..2ecdc3f70a7 100644 --- a/src/gallium/drivers/r600/sfn/sfn_nir_lower_tess_io.cpp +++ b/src/gallium/drivers/r600/sfn/sfn_nir_lower_tess_io.cpp @@ -34,34 +34,30 @@ emit_load_param_base(nir_builder *b, nir_intrinsic_op op) return &result->dest.ssa; } -static int get_tcs_varying_offset(nir_shader *nir, nir_variable_mode mode, - unsigned index) +static int get_tcs_varying_offset(nir_intrinsic_instr *op) { - nir_foreach_variable_with_modes(var, nir, mode) { - if (var->data.driver_location == index) { - switch (var->data.location) { - case VARYING_SLOT_POS: - return 0; - case VARYING_SLOT_PSIZ: - return 0x10; - case VARYING_SLOT_CLIP_DIST0: - return 0x20; - case VARYING_SLOT_CLIP_DIST1: - return 0x30; - case VARYING_SLOT_TESS_LEVEL_OUTER: - return 0; - case VARYING_SLOT_TESS_LEVEL_INNER: - return 0x10; - default: - if (var->data.location >= VARYING_SLOT_VAR0 && - var->data.location <= VARYING_SLOT_VAR31) - return 0x10 * (var->data.location - VARYING_SLOT_VAR0) + 0x40; + unsigned location = nir_intrinsic_io_semantics(op).location; - if (var->data.location >= VARYING_SLOT_PATCH0) { - return 0x10 * (var->data.location - VARYING_SLOT_PATCH0) + 0x20; - } - } - /* TODO: PATCH is missing */ + switch (location) { + case VARYING_SLOT_POS: + return 0; + case VARYING_SLOT_PSIZ: + return 0x10; + case VARYING_SLOT_CLIP_DIST0: + return 0x20; + case VARYING_SLOT_CLIP_DIST1: + return 0x30; + case VARYING_SLOT_TESS_LEVEL_OUTER: + return 0; + case VARYING_SLOT_TESS_LEVEL_INNER: + return 0x10; + default: + if (location >= VARYING_SLOT_VAR0 && + location <= VARYING_SLOT_VAR31) + return 0x10 * (location - VARYING_SLOT_VAR0) + 0x40; + + if (location >= VARYING_SLOT_PATCH0) { + return 0x10 * (location - VARYING_SLOT_PATCH0) + 0x20; } } return 0; @@ -94,7 +90,7 @@ emil_lsd_in_addr(nir_builder *b, nir_ssa_def *base, nir_ssa_def *patch_id, nir_i addr = r600_umad_24(b, nir_channel(b, base, 1), op->src[0].ssa, addr); - auto offset = nir_imm_int(b, get_tcs_varying_offset(b->shader, nir_var_shader_in, nir_intrinsic_base(op))); + auto offset = nir_imm_int(b, get_tcs_varying_offset(op)); auto idx2 = nir_src_as_const_value(op->src[1]); if (!idx2 || idx2->u32 != 0) @@ -112,8 +108,7 @@ emil_lsd_out_addr(nir_builder *b, nir_ssa_def *base, nir_ssa_def *patch_id, nir_ nir_channel(b, base, 2)); nir_ssa_def *addr2 = r600_umad_24(b, nir_channel(b, base, 1), op->src[src_offset].ssa, addr1); - - int offset = get_tcs_varying_offset(b->shader, mode, nir_intrinsic_base(op)); + int offset = get_tcs_varying_offset(op); return nir_iadd(b, nir_iadd(b, addr2, nir_ishl(b, op->src[src_offset + 1].ssa, nir_imm_int(b,4))), nir_imm_int(b, offset)); @@ -185,10 +180,9 @@ emit_store_lds(nir_builder *b, nir_intrinsic_instr *op, nir_ssa_def *addr) } static nir_ssa_def * -emil_tcs_io_offset(nir_builder *b, nir_ssa_def *addr, nir_intrinsic_instr *op, nir_variable_mode mode, int src_offset) +emil_tcs_io_offset(nir_builder *b, nir_ssa_def *addr, nir_intrinsic_instr *op, int src_offset) { - - int offset = get_tcs_varying_offset(b->shader, mode, nir_intrinsic_base(op)); + int offset = get_tcs_varying_offset(op); return nir_iadd(b, nir_iadd(b, addr, nir_ishl(b, op->src[src_offset].ssa, nir_imm_int(b,4))), nir_imm_int(b, offset)); @@ -264,20 +258,20 @@ r600_lower_tess_io_impl(nir_builder *b, nir_instr *instr, enum pipe_prim_type pr nir_build_alu(b, nir_op_umul24, nir_channel(b, load_out_param_base, 1), rel_patch_id, NULL, NULL); - addr = emil_tcs_io_offset(b, addr, op, nir_var_shader_out, 1); + addr = emil_tcs_io_offset(b, addr, op, 1); emit_store_lds(b, op, addr); nir_instr_remove(instr); return true; } case nir_intrinsic_load_output: { nir_ssa_def *addr = r600_tcs_base_address(b, load_out_param_base, rel_patch_id); - addr = emil_tcs_io_offset(b, addr, op, nir_var_shader_out, 0); + addr = emil_tcs_io_offset(b, addr, op, 0); replace_load_instr(b, op, addr); return true; } case nir_intrinsic_load_input: { nir_ssa_def *addr = r600_tcs_base_address(b, load_in_param_base, rel_patch_id); - addr = emil_tcs_io_offset(b, addr, op, nir_var_shader_in, 0); + addr = emil_tcs_io_offset(b, addr, op, 0); replace_load_instr(b, op, addr); return true; }