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r600: fix typos
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22432>
This commit is contained in:
Harri Nieminen
Marge Bot
parent
7851b6fd48
commit
45e09d5bb9
14 changed files with 31 additions and 31 deletions
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@ -57,7 +57,7 @@
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RAT0 is for global binding write
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VTX1 is for global binding read
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for wrting images RAT1...
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for writing images RAT1...
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for reading images TEX2...
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TEX2-RAT1 is paired
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@ -1155,7 +1155,7 @@ void evergreen_init_atom_start_compute_cs(struct r600_context *rctx)
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r600_store_value(cb, 0);
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/* R_008C28_SQ_STACK_RESOURCE_MGMT_3
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* Set the Contol Flow stack entries to 0 for the HS stage, and
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* Set the Control Flow stack entries to 0 for the HS stage, and
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* set it to the maximum value for the CS (aka LS) stage. */
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r600_store_value(cb,
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S_008C28_NUM_LS_STACK_ENTRIES(num_stack_entries));
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@ -3881,7 +3881,7 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx,
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slice_tile_max = (rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.u.legacy.level[src_level].nblk_y) / (8*8);
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slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
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/* linear height must be the same as the slice tile max height, it's ok even
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* if the linear destination/source have smaller heigh as the size of the
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* if the linear destination/source have smaller height as the size of the
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* dma packet will be using the copy_height which is always smaller or equal
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* to the linear height
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*/
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@ -3906,7 +3906,7 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx,
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slice_tile_max = (rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[dst_level].nblk_y) / (8*8);
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slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
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/* linear height must be the same as the slice tile max height, it's ok even
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* if the linear destination/source have smaller heigh as the size of the
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* if the linear destination/source have smaller height as the size of the
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* dma packet will be using the copy_height which is always smaller or equal
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* to the linear height
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*/
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@ -295,7 +295,7 @@ r600_bytecode_write_export_ack_type(struct r600_bytecode *bc, bool indirect)
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}
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}
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/* alu instructions that can ony exits once per group */
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/* alu instructions that can only exits once per group */
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static int is_alu_once_inst(struct r600_bytecode_alu *alu)
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{
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return r600_isa_alu(alu->op)->flags & (AF_KILL | AF_PRED) || alu->is_lds_idx_op || alu->op == ALU_OP0_GROUP_BARRIER;
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@ -611,7 +611,7 @@ static int check_and_set_bank_swizzle(const struct r600_bytecode *bc,
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return 0;
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/* Just check every possible combination of bank swizzle.
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* Not very efficent, but works on the first try in most of the cases. */
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* Not very efficient, but works on the first try in most of the cases. */
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for (i = 0; i < 4; i++)
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if (!slots[i] || !slots[i]->bank_swizzle_force || slots[i]->is_lds_idx_op)
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bank_swizzle[i] = SQ_ALU_VEC_012;
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@ -962,7 +962,7 @@ static int merge_inst_groups(struct r600_bytecode *bc, struct r600_bytecode_alu
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if (!prev[j] || !alu_writes(prev[j]))
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continue;
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/* If it's relative then we can't determin which gpr is really used. */
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/* If it's relative then we can't determine which gpr is really used. */
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if (prev[j]->dst.chan == alu->src[src].chan &&
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(prev[j]->dst.sel == alu->src[src].sel ||
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prev[j]->dst.rel || alu->src[src].rel))
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@ -982,7 +982,7 @@ static int merge_inst_groups(struct r600_bytecode *bc, struct r600_bytecode_alu
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/* looks like everything worked out right, apply the changes */
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/* undo adding previus literals */
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/* undo adding previous literals */
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bc->cf_last->ndw -= align(prev_nliteral, 2);
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/* sort instructions */
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@ -279,7 +279,7 @@ struct r600_bytecode {
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unsigned r6xx_nop_after_rel_dst;
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bool index_loaded[2];
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unsigned index_reg[2]; /* indexing register CF_INDEX_[01] */
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unsigned index_reg_chan[2]; /* indexing register chanel CF_INDEX_[01] */
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unsigned index_reg_chan[2]; /* indexing register channel CF_INDEX_[01] */
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unsigned debug_id;
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struct r600_isa* isa;
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struct r600_bytecode_output pending_outputs[5];
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@ -199,7 +199,7 @@ static void r600_blit_decompress_depth(struct pipe_context *ctx,
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}
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}
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/* reenable compression in DB_RENDER_CONTROL */
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/* re-enable compression in DB_RENDER_CONTROL */
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rctx->db_misc_state.flush_depthstencil_through_cb = false;
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r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
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}
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@ -271,7 +271,7 @@ void r600_invalidate_resource(struct pipe_context *ctx,
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struct r600_common_context *rctx = (struct r600_common_context*)ctx;
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struct r600_resource *rbuffer = r600_resource(resource);
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/* We currently only do anyting here for buffers */
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/* We currently only do anything here for buffers */
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if (resource->target == PIPE_BUFFER)
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(void)r600_invalidate_buffer(rctx, rbuffer);
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}
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@ -167,7 +167,7 @@ void r600_flush_emit(struct r600_context *rctx)
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if (rctx->b.flags & R600_CONTEXT_INV_CONST_CACHE) {
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/* Direct constant addressing uses the shader cache.
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* Indirect contant addressing uses the vertex cache. */
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* Indirect constant addressing uses the vertex cache. */
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cp_coher_cntl |= S_0085F0_SH_ACTION_ENA(1) |
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(rctx->has_vertex_cache ? S_0085F0_VC_ACTION_ENA(1)
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: S_0085F0_TC_ACTION_ENA(1));
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@ -421,7 +421,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
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case PIPE_CAP_TWO_SIDED_COLOR:
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return !is_nir_enabled(&rscreen->b);
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case PIPE_CAP_INT64_DIVMOD:
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/* it is actually not supported, but the nir lowering handles this corectly wheras
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/* it is actually not supported, but the nir lowering handles this correctly whereas
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* the glsl lowering path seems to not initialize the buildins correctly.
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*/
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return is_nir_enabled(&rscreen->b);
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@ -148,7 +148,7 @@ struct r600_resource {
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* streamout, DMA, or as a random access target). The rest of
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* the buffer is considered invalid and can be mapped unsynchronized.
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*
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* This allows unsychronized mapping of a buffer range which hasn't
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* This allows unsynchronized mapping of a buffer range which hasn't
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* been used yet. It's for applications which forget to use
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* the unsynchronized map flag and expect the driver to figure it out.
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*/
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@ -218,7 +218,7 @@ int r600_pipe_shader_create(struct pipe_context *ctx,
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sel->nir_blob = NULL;
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}
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sel->nir = tgsi_to_nir(sel->tokens, ctx->screen, true);
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/* Lower int64 ops because we have some r600 build-in shaders that use it */
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/* Lower int64 ops because we have some r600 built-in shaders that use it */
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if (nir_options->lower_int64_options) {
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NIR_PASS_V(sel->nir, nir_lower_regs_to_ssa);
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NIR_PASS_V(sel->nir, nir_lower_alu_to_scalar, r600_lower_to_scalar_instr_filter, NULL);
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@ -3402,7 +3402,7 @@ static int r600_emit_tess_factor(struct r600_shader_ctx *ctx)
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* calculated from the MBCNT instructions.
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* Then the shader engine ID is multiplied by 256,
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* and the wave id is added.
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* Then the result is multipled by 64 and thread id is
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* Then the result is multiplied by 64 and thread id is
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* added.
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*/
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static int load_thread_id_gpr(struct r600_shader_ctx *ctx)
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@ -8374,7 +8374,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
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if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
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inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY)
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/* make sure array index selector is 0, this is just a safety
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* precausion because TGSI seems to emit something strange here */
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* precaution because TGSI seems to emit something strange here */
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t->src_sel_z = 4;
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else
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t->src_sel_z = inst->TexOffsets[0].SwizzleZ;
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@ -2879,7 +2879,7 @@ static boolean r600_dma_copy_tile(struct r600_context *rctx,
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slice_tile_max = (rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.u.legacy.level[src_level].nblk_y) / (8*8);
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slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
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/* linear height must be the same as the slice tile max height, it's ok even
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* if the linear destination/source have smaller heigh as the size of the
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* if the linear destination/source have smaller height as the size of the
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* dma packet will be using the copy_height which is always smaller or equal
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* to the linear height
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*/
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@ -2898,7 +2898,7 @@ static boolean r600_dma_copy_tile(struct r600_context *rctx,
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slice_tile_max = (rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[dst_level].nblk_y) / (8*8);
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slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
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/* linear height must be the same as the slice tile max height, it's ok even
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* if the linear destination/source have smaller heigh as the size of the
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* if the linear destination/source have smaller height as the size of the
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* dma packet will be using the copy_height which is always smaller or equal
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* to the linear height
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*/
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@ -3042,9 +3042,9 @@ void r600_init_state_functions(struct r600_context *rctx)
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unsigned id = 1;
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unsigned i;
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/* !!!
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* To avoid GPU lockup registers must be emited in a specific order
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* To avoid GPU lockup registers must be emitted in a specific order
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* (no kidding ...). The order below is important and have been
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* partialy infered from analyzing fglrx command stream.
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* partially inferred from analyzing fglrx command stream.
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*
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* Don't reorder atom without carefully checking the effect (GPU lockup
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* or piglit regression).
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@ -3058,8 +3058,8 @@ void r600_init_state_functions(struct r600_context *rctx)
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r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0);
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r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0);
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/* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
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* does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
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/* sampler must be emitted before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
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* does not take effect (TA_CNTL_AUX emitted by r600_emit_seamless_cube_map)
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*/
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r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0);
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r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0);
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@ -1970,7 +1970,7 @@ static bool r600_update_derived_state(struct r600_context *rctx)
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* it will therefore overwrite the VS slots. If it now gets disabled,
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* the VS needs to rebind all buffer/resource/sampler slots - not only
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* has TES overwritten the corresponding slots, but when the VS was
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* operating as LS the things with correpsonding dirty bits got bound
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* operating as LS the things with corresponding dirty bits got bound
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* to LS slots and won't reflect what is dirty as VS stage even if the
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* TES didn't overwrite it. The story for re-enabled TES is similar.
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* In any case, we're not allowed to submit any TES state when
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@ -2795,7 +2795,7 @@ uint32_t r600_translate_texformat(struct pipe_screen *screen,
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* not divisible by 8.
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* Mesa conversion functions don't swap bits for those formats, and because
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* we transmit this over a serial bus to the GPU (PCIe), the
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* bit-endianess is important!!!
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* bit-endianness is important!!!
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* In case we have an "opposite" format, just use that for the swizzling
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* information. If we don't have such an "opposite" format, we need
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* to use a fixed swizzle info instead (see below)
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@ -3272,7 +3272,7 @@ uint32_t r600_colorformat_endian_swap(uint32_t colorformat, bool do_endian_swap)
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/*
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* No need to do endian swaps on array formats,
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* as mesa<-->pipe formats conversion take into account
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* the endianess
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* the endianness
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*/
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return ENDIAN_NONE;
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@ -3287,7 +3287,7 @@ uint32_t r600_colorformat_endian_swap(uint32_t colorformat, bool do_endian_swap)
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/*
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* No need to do endian swaps on array formats,
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* as mesa<-->pipe formats conversion take into account
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* the endianess
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* the endianness
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*/
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return ENDIAN_NONE;
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@ -1366,7 +1366,7 @@ void *r600_texture_transfer_map(struct pipe_context *ctx,
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* First downsample the depth buffer to a temporary texture,
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* then decompress the temporary one to staging.
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*
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* Only the region being mapped is transfered.
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* Only the region being mapped is transferred.
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*/
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struct pipe_resource resource;
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@ -1895,7 +1895,7 @@ r600_texture_from_memobj(struct pipe_screen *screen,
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* surface pitch isn't correctly aligned by default.
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*
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* In order to support it correctly we require multi-image
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* metadata to be syncrhonized between radv and radeonsi. The
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* metadata to be synchronized between radv and radeonsi. The
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* semantics of associating multiple image metadata to a memory
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* object on the vulkan export side are not concretely defined
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* either.
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@ -295,7 +295,7 @@ static unsigned calc_dpb_size(struct ruvd_decoder *dec)
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dpb_size += align(width_in_mb * height_in_mb * 32, alignment);
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}
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} else {
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// the firmware seems to allways assume a minimum of ref frames
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// the firmware seems to always assume a minimum of ref frames
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max_references = MAX2(NUM_H264_REFS, max_references);
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// reference picture buffer
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dpb_size = image_size * max_references;
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@ -310,7 +310,7 @@ static unsigned calc_dpb_size(struct ruvd_decoder *dec)
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}
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case PIPE_VIDEO_FORMAT_VC1:
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// the firmware seems to allways assume a minimum of ref frames
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// the firmware seems to always assume a minimum of ref frames
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max_references = MAX2(NUM_VC1_REFS, max_references);
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// reference picture buffer
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