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tu: Add more info to ldg inline uniform path

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This will let us push the ldg into the preamble.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
This commit is contained in:
Connor Abbott 2024-02-01 06:42:59 -05:00 • committed by Marge Bot
parent b87b8fdf73
commit 45c71803f9
2 changed files with 13 additions and 2 deletions
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3
src/compiler/nir/nir_intrinsics.py
View file

@ -1320,7 +1320,8 @@ load("shared_ir3", [1], [BASE, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE])
store("global_ir3", [2, 1], indices=[ACCESS, ALIGN_MUL, ALIGN_OFFSET])
# src[] = { address(vec2 of hi+lo uint32_t), offset }.
# const_index[] = { access, align_mul, align_offset }
load("global_ir3", [2, 1], indices=[ACCESS, ALIGN_MUL, ALIGN_OFFSET], flags=[CAN_ELIMINATE])
# the alignment applies to the base address
load("global_ir3", [2, 1], indices=[ACCESS, ALIGN_MUL, ALIGN_OFFSET, RANGE_BASE, RANGE], flags=[CAN_ELIMINATE])
# IR3-specific bindless handle specifier. Similar to vulkan_resource_index, but
# without the binding because the hardware expects a single flattened index

12
src/freedreno/vulkan/tu_shader.cc
View file

@ -676,12 +676,14 @@ lower_inline_ubo(nir_builder *b, nir_intrinsic_instr *intrin, void *cb_data)
struct tu_const_state *const_state = &shader->const_state;
unsigned base = UINT_MAX;
unsigned range;
bool use_load = false;
for (unsigned i = 0; i < const_state->num_inline_ubos; i++) {
if (const_state->ubos[i].base == binding.desc_set &&
const_state->ubos[i].offset == binding_layout->offset) {
base = const_state->ubos[i].const_offset_vec4 * 4;
use_load = const_state->ubos[i].push_address;
range = const_state->ubos[i].size_vec4 * 4;
break;
}
}
@ -706,7 +708,15 @@ lower_inline_ubo(nir_builder *b, nir_intrinsic_instr *intrin, void *cb_data)
nir_load_uniform(b, 2, 32, nir_imm_int(b, 0), .base = base);
val = nir_load_global_ir3(b, intrin->num_components,
intrin->def.bit_size,
base_addr, nir_ishr_imm(b, offset, 2));
base_addr, nir_ishr_imm(b, offset, 2),
.access =
(enum gl_access_qualifier)(
(enum gl_access_qualifier)(ACCESS_NON_WRITEABLE | ACCESS_CAN_REORDER) |
ACCESS_CAN_SPECULATE),
.align_mul = 16,
.align_offset = 0,
.range_base = 0,
.range = range);
} else {
val = nir_load_uniform(b, intrin->num_components,
intrin->def.bit_size,