diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c index 25c9c0190b8..d51c180680f 100644 --- a/src/intel/vulkan/anv_blorp.c +++ b/src/intel/vulkan/anv_blorp.c @@ -542,6 +542,8 @@ anv_add_buffer_write_pending_bits(struct anv_cmd_buffer *cmd_buffer, const struct intel_device_info *devinfo = cmd_buffer->device->info; cmd_buffer->state.pending_query_bits |= + (cmd_buffer->queue_family->queueFlags & VK_QUEUE_GRAPHICS_BIT) == 0 ? + ANV_QUERY_COMPUTE_WRITES_PENDING_BITS : ANV_QUERY_RENDER_TARGET_WRITES_PENDING_BITS(devinfo); } @@ -562,9 +564,9 @@ void anv_CmdCopyImageToBuffer2( &pCopyImageToBufferInfo->pRegions[r], false); } - anv_blorp_batch_finish(&batch); - anv_add_buffer_write_pending_bits(cmd_buffer, "after copy image to buffer"); + + anv_blorp_batch_finish(&batch); } static bool @@ -787,9 +789,9 @@ void anv_CmdCopyBuffer2( &pCopyBufferInfo->pRegions[r]); } - anv_blorp_batch_finish(&batch); - anv_add_buffer_write_pending_bits(cmd_buffer, "after copy buffer"); + + anv_blorp_batch_finish(&batch); } @@ -849,9 +851,9 @@ void anv_CmdUpdateBuffer( pData = (void *)pData + copy_size; } - anv_blorp_batch_finish(&batch); - anv_add_buffer_write_pending_bits(cmd_buffer, "update buffer"); + + anv_blorp_batch_finish(&batch); } void @@ -960,7 +962,6 @@ void anv_CmdFillBuffer( fillSize, data); anv_add_buffer_write_pending_bits(cmd_buffer, "after fill buffer"); - } void anv_CmdClearColorImage( diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index 474cf81e1f0..b8947b9807c 100644 --- a/src/intel/vulkan/anv_private.h +++ b/src/intel/vulkan/anv_private.h @@ -2205,11 +2205,13 @@ enum anv_pipe_bits { * based on PIPE_CONTROL emissions. */ enum anv_query_bits { - ANV_QUERY_RENDER_TARGET_WRITES_RT_FLUSH = (1 << 0), + ANV_QUERY_WRITES_RT_FLUSH = (1 << 0), - ANV_QUERY_RENDER_TARGET_WRITES_TILE_FLUSH = (1 << 1), + ANV_QUERY_WRITES_TILE_FLUSH = (1 << 1), - ANV_QUERY_RENDER_TARGET_WRITES_CS_STALL = (1 << 2), + ANV_QUERY_WRITES_CS_STALL = (1 << 2), + + ANV_QUERY_WRITES_DATA_FLUSH = (1 << 3), }; /* Things we need to flush before accessing query data using the command @@ -2224,17 +2226,24 @@ enum anv_query_bits { */ #define ANV_QUERY_RENDER_TARGET_WRITES_PENDING_BITS(devinfo) \ (((devinfo->verx10 >= 120 && \ - devinfo->verx10 < 125) ? ANV_QUERY_RENDER_TARGET_WRITES_TILE_FLUSH : 0) | \ - ANV_QUERY_RENDER_TARGET_WRITES_RT_FLUSH | \ - ANV_QUERY_RENDER_TARGET_WRITES_CS_STALL) + devinfo->verx10 < 125) ? ANV_QUERY_WRITES_TILE_FLUSH : 0) | \ + ANV_QUERY_WRITES_RT_FLUSH | \ + ANV_QUERY_WRITES_CS_STALL) +#define ANV_QUERY_COMPUTE_WRITES_PENDING_BITS \ + (ANV_QUERY_WRITES_DATA_FLUSH | \ + ANV_QUERY_WRITES_CS_STALL) #define ANV_PIPE_QUERY_BITS(pending_query_bits) ( \ - ((pending_query_bits & ANV_QUERY_RENDER_TARGET_WRITES_RT_FLUSH) ? \ + ((pending_query_bits & ANV_QUERY_WRITES_RT_FLUSH) ? \ ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT : 0) | \ - ((pending_query_bits & ANV_QUERY_RENDER_TARGET_WRITES_TILE_FLUSH) ? \ + ((pending_query_bits & ANV_QUERY_WRITES_TILE_FLUSH) ? \ ANV_PIPE_TILE_CACHE_FLUSH_BIT : 0) | \ - ((pending_query_bits & ANV_QUERY_RENDER_TARGET_WRITES_CS_STALL) ? \ - ANV_PIPE_CS_STALL_BIT : 0)) + ((pending_query_bits & ANV_QUERY_WRITES_CS_STALL) ? \ + ANV_PIPE_CS_STALL_BIT : 0) | \ + ((pending_query_bits & ANV_QUERY_WRITES_DATA_FLUSH) ? \ + (ANV_PIPE_DATA_CACHE_FLUSH_BIT | \ + ANV_PIPE_HDC_PIPELINE_FLUSH_BIT | \ + ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT) : 0)) #define ANV_PIPE_FLUSH_BITS ( \ ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \ diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 674203a433c..5c4a4c0fae8 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -1631,16 +1631,22 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch, */ if (query_bits != NULL) { if (bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT) - *query_bits &= ~ANV_QUERY_RENDER_TARGET_WRITES_RT_FLUSH; + *query_bits &= ~ANV_QUERY_WRITES_RT_FLUSH; if (bits & ANV_PIPE_TILE_CACHE_FLUSH_BIT) - *query_bits &= ~ANV_QUERY_RENDER_TARGET_WRITES_TILE_FLUSH; + *query_bits &= ~ANV_QUERY_WRITES_TILE_FLUSH; + + if ((bits & ANV_PIPE_DATA_CACHE_FLUSH_BIT) && + (bits & ANV_PIPE_HDC_PIPELINE_FLUSH_BIT) && + (bits & ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT)) + *query_bits &= ~ANV_QUERY_WRITES_TILE_FLUSH; /* Once RT/TILE have been flushed, we can consider the CS_STALL flush */ - if ((*query_bits & (ANV_QUERY_RENDER_TARGET_WRITES_TILE_FLUSH | - ANV_QUERY_RENDER_TARGET_WRITES_RT_FLUSH)) == 0 && + if ((*query_bits & (ANV_QUERY_WRITES_TILE_FLUSH | + ANV_QUERY_WRITES_RT_FLUSH | + ANV_QUERY_WRITES_DATA_FLUSH)) == 0 && (bits & (ANV_PIPE_END_OF_PIPE_SYNC_BIT | ANV_PIPE_CS_STALL_BIT))) - *query_bits &= ~ANV_QUERY_RENDER_TARGET_WRITES_CS_STALL; + *query_bits &= ~ANV_QUERY_WRITES_CS_STALL; } bits &= ~(ANV_PIPE_FLUSH_BITS | ANV_PIPE_STALL_BITS | diff --git a/src/intel/vulkan/genX_query.c b/src/intel/vulkan/genX_query.c index 6c099a4e331..7f1c0464645 100644 --- a/src/intel/vulkan/genX_query.c +++ b/src/intel/vulkan/genX_query.c @@ -1522,15 +1522,22 @@ void genX(CmdCopyQueryPoolResults)( * command streamer. */ if (cmd_buffer->state.pending_query_bits & - ANV_QUERY_RENDER_TARGET_WRITES_RT_FLUSH) + ANV_QUERY_WRITES_RT_FLUSH) needed_flushes |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT; if (cmd_buffer->state.pending_query_bits & - ANV_QUERY_RENDER_TARGET_WRITES_TILE_FLUSH) + ANV_QUERY_WRITES_TILE_FLUSH) needed_flushes |= ANV_PIPE_TILE_CACHE_FLUSH_BIT; if (cmd_buffer->state.pending_query_bits & - ANV_QUERY_RENDER_TARGET_WRITES_CS_STALL) + ANV_QUERY_WRITES_DATA_FLUSH) { + needed_flushes |= (ANV_PIPE_DATA_CACHE_FLUSH_BIT | + ANV_PIPE_HDC_PIPELINE_FLUSH_BIT | + ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT); + } + + if (cmd_buffer->state.pending_query_bits & + ANV_QUERY_WRITES_CS_STALL) needed_flushes |= ANV_PIPE_CS_STALL_BIT; /* Occlusion & timestamp queries are written using a PIPE_CONTROL and