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r600g: don't emit surface_sync after FLUSH_AND_INV_EVENT

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It shouldn't be needed since the FLUSH_AND_INV_EVENT has already
made sure the destination caches are flushed.  Additionally,
we didn't previously emit the surface_sync until this commit:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e5e4c07e7964a3258ed02b530bcdc24c0650204b
Emitting them together causes hangs in compute on cayman/TN
and hangs in Heaven on evergreen.

Note: this patch is a candidate for the 9.1 branch, but requires:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=156bcca62c9f4e79e78929f72bc085757f36a65a
as well.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2013-05-03 09:56:31 -04:00
parent 41005d7bd2
commit 4539f8e20a
1 changed files with 0 additions and 26 deletions
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26
src/gallium/drivers/r600/r600_hw_context.c
View file

@ -226,32 +226,6 @@ void r600_flush_emit(struct r600_context *rctx)
if (rctx->flags & R600_CONTEXT_FLUSH_AND_INV) { if (rctx->flags & R600_CONTEXT_FLUSH_AND_INV) {
cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0); cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0); cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
if (rctx->chip_class >= EVERGREEN) {
/* We were previously setting the CB and DB bits on
* cp_coher_cntl, but this is unnecessary since
* we are emitting the
* EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT packet.
* Setting the CB bits was causing lockups when using
* compute on cayman.
*
* XXX: Do even need to emit a surface sync packet here?
* Prior to e5e4c07e7964a3258ed02b530bcdc24c0650204b
* surface sync was not being emitted with the
* R600_CONTEXT_FLUSH_AND_INV flag.
*/
cp_coher_cntl = S_0085F0_TC_ACTION_ENA(1) |
S_0085F0_DB_ACTION_ENA(1) |
S_0085F0_SH_ACTION_ENA(1) |
S_0085F0_SMX_ACTION_ENA(1) |
S_0085F0_FULL_CACHE_ENA(1);
} else {
cp_coher_cntl = S_0085F0_SMX_ACTION_ENA(1) |
S_0085F0_SH_ACTION_ENA(1) |
S_0085F0_VC_ACTION_ENA(1) |
S_0085F0_TC_ACTION_ENA(1) |
S_0085F0_FULL_CACHE_ENA(1);
}
emit_flush = 1;
} }
if (rctx->flags & R600_CONTEXT_INVAL_READ_CACHES) { if (rctx->flags & R600_CONTEXT_INVAL_READ_CACHES) {