From 45319cb2535e1995143156d151dc9afa88dee2df Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Thu, 29 Aug 2024 15:33:47 +0200 Subject: [PATCH] radv: specialize push constant stages with DGC Even if the layout declares using push constant for more stages than needed, upload_sgpr/inline_sgpr will prevent the DGC prepare shader to emit them because it's initialized to 0. Signed-off-by: Samuel Pitoiset Part-of: --- .../vulkan/radv_device_generated_commands.c | 48 ++++--------------- .../vulkan/radv_device_generated_commands.h | 1 + 2 files changed, 10 insertions(+), 39 deletions(-) diff --git a/src/amd/vulkan/radv_device_generated_commands.c b/src/amd/vulkan/radv_device_generated_commands.c index e9a1633519b..5fe38bbfdc9 100644 --- a/src/amd/vulkan/radv_device_generated_commands.c +++ b/src/amd/vulkan/radv_device_generated_commands.c @@ -424,8 +424,6 @@ struct radv_dgc_params { uint16_t vbo_reg; uint8_t dynamic_vs_input; - uint16_t push_constant_stages; - uint8_t use_preamble; /* For conditional rendering on ACE. */ @@ -1156,22 +1154,6 @@ dgc_emit_index_buffer(struct dgc_cmdbuf *cs, nir_def *stream_addr, nir_variable /** * Emit VK_INDIRECT_COMMANDS_TOKEN_TYPE_PUSH_CONSTANT_NV. */ -static nir_def * -dgc_get_push_constant_stages(struct dgc_cmdbuf *cs, nir_def *stream_addr) -{ - const struct radv_indirect_command_layout *layout = cs->layout; - nir_builder *b = cs->b; - - if (layout->bind_pipeline) { - nir_def *pipeline_va = dgc_get_pipeline_va(cs, stream_addr); - - nir_def *has_push_constant = nir_ine_imm(b, load_metadata32(b, push_const_sgpr), 0); - return nir_bcsel(b, has_push_constant, nir_imm_int(b, VK_SHADER_STAGE_COMPUTE_BIT), nir_imm_int(b, 0)); - } else { - return load_param16(b, push_constant_stages); - } -} - static nir_def * dgc_get_upload_sgpr(struct dgc_cmdbuf *cs, nir_def *stream_addr, nir_def *param_buf, nir_def *param_offset, gl_shader_stage stage) @@ -1346,17 +1328,13 @@ dgc_emit_push_constant_for_stage(struct dgc_cmdbuf *cs, nir_def *stream_addr, co static void dgc_emit_push_constant(struct dgc_cmdbuf *cs, nir_def *stream_addr, VkShaderStageFlags stages) { + const struct radv_indirect_command_layout *layout = cs->layout; const struct dgc_pc_params params = dgc_get_pc_params(cs); nir_builder *b = cs->b; - nir_def *push_constant_stages = dgc_get_push_constant_stages(cs, stream_addr); - radv_foreach_stage(s, stages) + radv_foreach_stage(s, stages & layout->push_constant_stages) { - nir_push_if(b, nir_test_mask(b, push_constant_stages, mesa_to_vk_shader_stage(s))); - { - dgc_emit_push_constant_for_stage(cs, stream_addr, ¶ms, s); - } - nir_pop_if(b, NULL); + dgc_emit_push_constant_for_stage(cs, stream_addr, ¶ms, s); } nir_def *const_copy = dgc_push_constant_needs_copy(cs, stream_addr); @@ -2002,15 +1980,9 @@ build_dgc_prepare_shader(struct radv_device *dev, struct radv_indirect_command_l nir_imul(&b, load_param32(&b, upload_stride), sequence_id)); nir_store_var(&b, cmd_buf.upload_offset, upload_offset_init, 0x1); - if (layout->push_constant_mask) { - nir_def *push_constant_stages = dgc_get_push_constant_stages(&cmd_buf, stream_addr); - - nir_push_if(&b, nir_test_mask(&b, push_constant_stages, VK_SHADER_STAGE_TASK_BIT_EXT)); - { - const struct dgc_pc_params params = dgc_get_pc_params(&cmd_buf); - dgc_emit_push_constant_for_stage(&cmd_buf, stream_addr, ¶ms, MESA_SHADER_TASK); - } - nir_pop_if(&b, NULL); + if (layout->push_constant_mask && (layout->push_constant_stages & VK_SHADER_STAGE_TASK_BIT_EXT)) { + const struct dgc_pc_params params = dgc_get_pc_params(&cmd_buf); + dgc_emit_push_constant_for_stage(&cmd_buf, stream_addr, ¶ms, MESA_SHADER_TASK); } dgc_emit_draw_mesh_tasks_ace(&cmd_buf, stream_addr); @@ -2171,6 +2143,7 @@ radv_CreateIndirectCommandsLayoutNV(VkDevice _device, const VkIndirectCommandsLa layout->push_constant_offsets[j] = pCreateInfo->pTokens[i].offset + k * 4; } layout->push_constant_size = pipeline_layout->push_constant_size; + layout->push_constant_stages = pCreateInfo->pTokens[i].pushconstantShaderStageFlags; assert(!pipeline_layout->dynamic_offset_count); break; } @@ -2516,10 +2489,11 @@ radv_prepare_dgc(struct radv_cmd_buffer *cmd_buffer, const VkGeneratedCommandsIn } if (layout->push_constant_mask) { - VkShaderStageFlags pc_stages = 0; uint32_t *desc = upload_data; upload_data = (char *)upload_data + ARRAY_SIZE(pipeline->shaders) * 12; + memset(desc, 0, ARRAY_SIZE(pipeline->shaders) * 12); + if (pipeline) { for (unsigned i = 0; i < ARRAY_SIZE(pipeline->shaders); ++i) { if (!pipeline->shaders[i]) @@ -2545,14 +2519,10 @@ radv_prepare_dgc(struct radv_cmd_buffer *cmd_buffer, const VkGeneratedCommandsIn desc[i * 3 + 2] = pipeline->shaders[i]->info.inline_push_constant_mask >> 32; } desc[i * 3] = upload_sgpr | (inline_sgpr << 16); - - pc_stages |= mesa_to_vk_shader_stage(i); } } } - params.push_constant_stages = pc_stages; - memcpy(upload_data, cmd_buffer->push_constants, layout->push_constant_size); upload_data = (char *)upload_data + layout->push_constant_size; } diff --git a/src/amd/vulkan/radv_device_generated_commands.h b/src/amd/vulkan/radv_device_generated_commands.h index 3af0eb15fe4..23c9e1a5edc 100644 --- a/src/amd/vulkan/radv_device_generated_commands.h +++ b/src/amd/vulkan/radv_device_generated_commands.h @@ -42,6 +42,7 @@ struct radv_indirect_command_layout { uint32_t bind_vbo_mask; uint32_t vbo_offsets[MAX_VBS]; + VkShaderStageFlags push_constant_stages; uint64_t push_constant_mask; uint32_t push_constant_offsets[MAX_PUSH_CONSTANTS_SIZE / 4]; uint32_t push_constant_size;