From 44f744be423116a3550d153fa9cebd5c9815b53a Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Fri, 9 Apr 2021 16:50:15 -0700 Subject: [PATCH] zink: Enable PIPE_CAP_PACKED_UNIFORMS. We already support everything necessary and just need to ask the frontend to DTRT. This makes UBO0 get more tightly packed, saving upload space, and allows for _mesa_optimize_state_parameters() as well. Reviewed-By: Mike Blumenkrantz Part-of: --- src/gallium/drivers/zink/zink_compiler.c | 3 ++- src/gallium/drivers/zink/zink_screen.c | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/zink/zink_compiler.c b/src/gallium/drivers/zink/zink_compiler.c index cff1f6d671f..a2edecb9806 100644 --- a/src/gallium/drivers/zink/zink_compiler.c +++ b/src/gallium/drivers/zink/zink_compiler.c @@ -387,6 +387,7 @@ zink_screen_init_compiler(struct zink_screen *screen) .lower_vector_cmp = true, .lower_int64_options = 0, .lower_doubles_options = ~nir_lower_fp64_full_software, + .lower_uniforms_to_ubo = true, .has_fsub = true, .has_isub = true, .lower_mul_2x32_64 = true, @@ -906,7 +907,7 @@ zink_shader_finalize(struct pipe_screen *pscreen, void *nirptr, bool optimize) tex_opts.lower_tg4_offsets = true; NIR_PASS_V(nir, nir_lower_tex, &tex_opts); } - NIR_PASS_V(nir, nir_lower_uniforms_to_ubo, false, false); + NIR_PASS_V(nir, nir_lower_uniforms_to_ubo, true, false); if (nir->info.stage == MESA_SHADER_GEOMETRY) NIR_PASS_V(nir, nir_lower_gs_intrinsics, nir_lower_gs_intrinsics_per_stream); optimize_nir(nir); diff --git a/src/gallium/drivers/zink/zink_screen.c b/src/gallium/drivers/zink/zink_screen.c index 40a46e9eae3..037500b22d5 100644 --- a/src/gallium/drivers/zink/zink_screen.c +++ b/src/gallium/drivers/zink/zink_screen.c @@ -251,6 +251,7 @@ zink_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_CLEAR_SCISSORED: case PIPE_CAP_INVALIDATE_BUFFER: case PIPE_CAP_PREFER_REAL_BUFFER_IN_CONSTBUF0: + case PIPE_CAP_PACKED_UNIFORMS: return 1; case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE: