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r600,compute: force tiling on 2D and 3D texture compute resources
To circumvent a problem occuring when LINEAR_ALIGNED array mode is selected on a TEXTURE_2D RAT. This configuration causes MEM_RAT STORE_TYPED to write to incorrect locations.
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be3622dce3
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44e90f2a55
1 changed files with 9 additions and 2 deletions
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@ -706,6 +706,7 @@ static unsigned r600_choose_tiling(struct r600_common_screen *rscreen,
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const struct pipe_resource *templ)
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{
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const struct util_format_description *desc = util_format_description(templ->format);
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bool force_tiling = templ->flags & R600_RESOURCE_FLAG_FORCE_TILING;
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/* MSAA resources must be 2D tiled. */
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if (templ->nr_samples > 1)
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@ -715,10 +716,16 @@ static unsigned r600_choose_tiling(struct r600_common_screen *rscreen,
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if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
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return RADEON_SURF_MODE_LINEAR_ALIGNED;
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/* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
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if (rscreen->chip_class >= R600 && rscreen->chip_class <= CAYMAN &&
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(templ->bind & PIPE_BIND_COMPUTE_RESOURCE) &&
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(templ->target == PIPE_TEXTURE_2D ||
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templ->target == PIPE_TEXTURE_3D))
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force_tiling = true;
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/* Handle common candidates for the linear mode.
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* Compressed textures must always be tiled. */
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if (!(templ->flags & R600_RESOURCE_FLAG_FORCE_TILING) &&
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!util_format_is_compressed(templ->format)) {
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if (!force_tiling && !util_format_is_compressed(templ->format)) {
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/* Not everything can be linear, so we cannot enforce it
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* for all textures. */
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if ((rscreen->debug_flags & DBG_NO_TILING) &&
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