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anv: rework gfx state emission (again)

Browse source 
Previously we had 2 stages :

  runtime -> precomputed values -> packing/emission

With this change we use 3 stages :

   runtime -> precomputed values -> packing -> emission

Now blorp & other changes to the pipeline should not retrigger
repacking of instructions.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36711>
This commit is contained in:
Lionel Landwerlin 2025-03-31 13:09:39 +03:00 • committed by Marge Bot
parent 5a2fb0da32
commit 44aaf88425
11 changed files with 1162 additions and 850 deletions
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13
src/intel/vulkan/anv_cmd_buffer.c
View file

@ -57,9 +57,8 @@ anv_cmd_state_init(struct anv_cmd_buffer *cmd_buffer)
state->compute.z_pass_async_compute_thread_limit = UINT8_MAX; state->compute.z_pass_async_compute_thread_limit = UINT8_MAX;
state->compute.np_z_async_throttle_settings = UINT8_MAX; state->compute.np_z_async_throttle_settings = UINT8_MAX;
memcpy(state->gfx.dyn_state.dirty, BITSET_COPY(state->gfx.dyn_state.pack_dirty,
cmd_buffer->device->gfx_dirty_state, cmd_buffer->device->gfx_dirty_state);
sizeof(state->gfx.dyn_state.dirty));
} }
static void static void
@ -516,25 +515,25 @@ anv_cmd_buffer_flush_pipeline_hw_state(struct anv_cmd_buffer *cmd_buffer,
assert(old_pipeline == NULL || \ assert(old_pipeline == NULL || \
old_pipeline->name.len == new_pipeline->name.len); \ old_pipeline->name.len == new_pipeline->name.len); \
/* Don't bother memcmp if the state is already dirty */ \ /* Don't bother memcmp if the state is already dirty */ \
if (!BITSET_TEST(hw_state->dirty, ANV_GFX_STATE_##bit) && \ if (!BITSET_TEST(hw_state->pack_dirty, ANV_GFX_STATE_##bit) && \
(old_pipeline == NULL || \ (old_pipeline == NULL || \
memcmp(&old_pipeline->batch_data[old_pipeline->name.offset], \ memcmp(&old_pipeline->batch_data[old_pipeline->name.offset], \
&new_pipeline->batch_data[new_pipeline->name.offset], \ &new_pipeline->batch_data[new_pipeline->name.offset], \
4 * new_pipeline->name.len) != 0)) \ 4 * new_pipeline->name.len) != 0)) \
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_##bit); \ BITSET_SET(hw_state->pack_dirty, ANV_GFX_STATE_##bit); \
} while (0) } while (0)
#define diff_var_state(bit, name) \ #define diff_var_state(bit, name) \
do { \ do { \
/* Don't bother memcmp if the state is already dirty */ \ /* Don't bother memcmp if the state is already dirty */ \
/* Also if the new state is empty, avoid marking dirty */ \ /* Also if the new state is empty, avoid marking dirty */ \
if (!BITSET_TEST(hw_state->dirty, ANV_GFX_STATE_##bit) && \ if (!BITSET_TEST(hw_state->pack_dirty, ANV_GFX_STATE_##bit) && \
new_pipeline->name.len != 0 && \ new_pipeline->name.len != 0 && \
(old_pipeline == NULL || \ (old_pipeline == NULL || \
old_pipeline->name.len != new_pipeline->name.len || \ old_pipeline->name.len != new_pipeline->name.len || \
memcmp(&old_pipeline->batch_data[old_pipeline->name.offset], \ memcmp(&old_pipeline->batch_data[old_pipeline->name.offset], \
&new_pipeline->batch_data[new_pipeline->name.offset], \ &new_pipeline->batch_data[new_pipeline->name.offset], \
4 * new_pipeline->name.len) != 0)) \ 4 * new_pipeline->name.len) != 0)) \
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_##bit); \ BITSET_SET(hw_state->pack_dirty, ANV_GFX_STATE_##bit); \
} while (0) } while (0)
#define assert_identical(bit, name) \ #define assert_identical(bit, name) \
do { \ do { \

4
src/intel/vulkan/anv_genX.h
View file

@ -131,7 +131,7 @@ genX(cmd_buffer_ensure_wa_14018283232)(struct anv_cmd_buffer *cmd_buffer,
if (intel_needs_workaround(cmd_buffer->device->info, 14018283232) && if (intel_needs_workaround(cmd_buffer->device->info, 14018283232) &&
hw_state->wa_14018283232_toggle != toggle) { hw_state->wa_14018283232_toggle != toggle) {
hw_state->wa_14018283232_toggle = toggle; hw_state->wa_14018283232_toggle = toggle;
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_WA_14018283232); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_WA_14018283232);
genX(batch_emit_wa_14018283232)(&cmd_buffer->batch); genX(batch_emit_wa_14018283232)(&cmd_buffer->batch);
} }
} }
@ -164,7 +164,7 @@ genX(cmd_buffer_set_coarse_pixel_active)(struct anv_cmd_buffer *cmd_buffer,
if (intel_needs_workaround(cmd_buffer->device->info, 18038825448) && if (intel_needs_workaround(cmd_buffer->device->info, 18038825448) &&
gfx->dyn_state.coarse_state != state) { gfx->dyn_state.coarse_state != state) {
gfx->dyn_state.coarse_state = state; gfx->dyn_state.coarse_state = state;
BITSET_SET(gfx->dyn_state.dirty, ANV_GFX_STATE_COARSE_STATE); BITSET_SET(gfx->dyn_state.emit_dirty, ANV_GFX_STATE_PS_EXTRA);
return true; return true;
} }
return false; return false;

28
src/intel/vulkan/anv_measure.c
View file

@ -154,16 +154,13 @@ anv_measure_start_snapshot(struct anv_cmd_buffer *cmd_buffer,
snapshot->renderpass = (type == INTEL_SNAPSHOT_COMPUTE) ? 0 snapshot->renderpass = (type == INTEL_SNAPSHOT_COMPUTE) ? 0
: measure->base.renderpass; : measure->base.renderpass;
if (type == INTEL_SNAPSHOT_COMPUTE && cmd_buffer->state.compute.base.pipeline) { if (type == INTEL_SNAPSHOT_COMPUTE && cmd_buffer->state.compute.shader) {
const struct anv_compute_pipeline *pipeline = snapshot->cs = cmd_buffer->state.compute.shader->prog_data->source_hash;
anv_pipeline_to_compute(cmd_buffer->state.compute.base.pipeline); } else if (type == INTEL_SNAPSHOT_DRAW) {
snapshot->cs = pipeline->cs->prog_data->source_hash; const struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
} else if (type == INTEL_SNAPSHOT_DRAW && cmd_buffer->state.gfx.base.pipeline) {
const struct anv_graphics_pipeline *pipeline =
anv_pipeline_to_graphics(cmd_buffer->state.gfx.base.pipeline);
#define SHADER_SOURCE_HASH(_name) \ #define SHADER_SOURCE_HASH(_name) \
(pipeline->base.shaders[MESA_SHADER_##VERTEX] ? \ (gfx->shaders[MESA_SHADER_##_name] ? \
pipeline->base.shaders[MESA_SHADER_##VERTEX]->prog_data->source_hash : 0) gfx->shaders[MESA_SHADER_##_name]->prog_data->source_hash : 0)
snapshot->vs = SHADER_SOURCE_HASH(VERTEX); snapshot->vs = SHADER_SOURCE_HASH(VERTEX);
snapshot->tcs = SHADER_SOURCE_HASH(TESS_CTRL); snapshot->tcs = SHADER_SOURCE_HASH(TESS_CTRL);
snapshot->tes = SHADER_SOURCE_HASH(TESS_EVAL); snapshot->tes = SHADER_SOURCE_HASH(TESS_EVAL);
@ -220,17 +217,12 @@ state_changed(struct anv_cmd_buffer *cmd_buffer,
return false; return false;
if (type == INTEL_SNAPSHOT_COMPUTE) { if (type == INTEL_SNAPSHOT_COMPUTE) {
const struct anv_compute_pipeline *cs_pipe = cs = cmd_buffer->state.compute.shader->prog_data->source_hash;
anv_pipeline_to_compute(cmd_buffer->state.compute.base.pipeline);
assert(cs_pipe);
cs = cs_pipe->cs->prog_data->source_hash;
} else if (type == INTEL_SNAPSHOT_DRAW) { } else if (type == INTEL_SNAPSHOT_DRAW) {
const struct anv_graphics_pipeline *gfx = const struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
anv_pipeline_to_graphics(cmd_buffer->state.gfx.base.pipeline);
assert(gfx);
#define SHADER_SOURCE_HASH(_name) \ #define SHADER_SOURCE_HASH(_name) \
(gfx->base.shaders[MESA_SHADER_##VERTEX] ? \ (gfx->shaders[MESA_SHADER_##_name] ? \
gfx->base.shaders[MESA_SHADER_##VERTEX]->prog_data->source_hash : 0) gfx->shaders[MESA_SHADER_##_name]->prog_data->source_hash : 0)
vs = SHADER_SOURCE_HASH(VERTEX); vs = SHADER_SOURCE_HASH(VERTEX);
tcs = SHADER_SOURCE_HASH(TESS_CTRL); tcs = SHADER_SOURCE_HASH(TESS_CTRL);
tes = SHADER_SOURCE_HASH(TESS_EVAL); tes = SHADER_SOURCE_HASH(TESS_EVAL);

87
src/intel/vulkan/anv_private.h
View file

@ -1534,11 +1534,9 @@ enum anv_gfx_state_bits {
ANV_GFX_STATE_TASK_SHADER, ANV_GFX_STATE_TASK_SHADER,
ANV_GFX_STATE_TASK_REDISTRIB, ANV_GFX_STATE_TASK_REDISTRIB,
/* Dynamic states */ /* Dynamic states */
ANV_GFX_STATE_BLEND_STATE, /* Just the dynamic state structure */ ANV_GFX_STATE_BLEND_STATE,
ANV_GFX_STATE_BLEND_STATE_PTR, /* The pointer to the dynamic state */
ANV_GFX_STATE_CLIP, ANV_GFX_STATE_CLIP,
ANV_GFX_STATE_CC_STATE, ANV_GFX_STATE_CC_STATE,
ANV_GFX_STATE_CC_STATE_PTR,
ANV_GFX_STATE_COARSE_PIXEL, ANV_GFX_STATE_COARSE_PIXEL,
ANV_GFX_STATE_CPS, ANV_GFX_STATE_CPS,
ANV_GFX_STATE_DEPTH_BOUNDS, ANV_GFX_STATE_DEPTH_BOUNDS,
@ -1558,7 +1556,6 @@ enum anv_gfx_state_bits {
ANV_GFX_STATE_VF_TOPOLOGY, ANV_GFX_STATE_VF_TOPOLOGY,
ANV_GFX_STATE_VFG, ANV_GFX_STATE_VFG,
ANV_GFX_STATE_VIEWPORT_CC, ANV_GFX_STATE_VIEWPORT_CC,
ANV_GFX_STATE_VIEWPORT_CC_PTR,
ANV_GFX_STATE_VIEWPORT_SF_CLIP, ANV_GFX_STATE_VIEWPORT_SF_CLIP,
ANV_GFX_STATE_WM, ANV_GFX_STATE_WM,
ANV_GFX_STATE_WM_DEPTH_STENCIL, ANV_GFX_STATE_WM_DEPTH_STENCIL,
@ -1569,7 +1566,6 @@ enum anv_gfx_state_bits {
ANV_GFX_STATE_TBIMR_TILE_PASS_INFO, ANV_GFX_STATE_TBIMR_TILE_PASS_INFO,
ANV_GFX_STATE_FS_MSAA_FLAGS, ANV_GFX_STATE_FS_MSAA_FLAGS,
ANV_GFX_STATE_TCS_INPUT_VERTICES, ANV_GFX_STATE_TCS_INPUT_VERTICES,
ANV_GFX_STATE_COARSE_STATE,
ANV_GFX_STATE_MESH_PROVOKING_VERTEX, ANV_GFX_STATE_MESH_PROVOKING_VERTEX,
ANV_GFX_STATE_MAX, ANV_GFX_STATE_MAX,
@ -1995,7 +1991,64 @@ struct anv_gfx_dynamic_state {
*/ */
enum anv_coarse_pixel_state coarse_state; enum anv_coarse_pixel_state coarse_state;
BITSET_DECLARE(dirty, ANV_GFX_STATE_MAX); /** Dirty bits of what needs to be repacked */
BITSET_DECLARE(pack_dirty, ANV_GFX_STATE_MAX);
struct {
uint32_t vf[2];
uint32_t vft[2];
uint32_t vfs[1];
uint32_t vfg[4];
uint32_t vf_sgvs[2];
uint32_t vf_sgvs_2[3];
uint32_t vf_sgvs_instancing[6];
uint32_t vf_sgvs_instancing_len;
uint32_t vf_component_packing[5];
uint32_t ib[5];
uint32_t so[5];
uint32_t so_decl_list[3 + 2 * 128];
uint32_t so_decl_list_len;
uint32_t clip[4];
uint32_t clip_mesh[2];
uint32_t sf_clip[2];
uint32_t cc_viewport[2];
uint32_t scissor[2];
uint32_t mesh_control[3];
uint32_t task_control[3];
uint32_t mesh_shader[8];
uint32_t task_shader[7];
uint32_t mesh_distrib[2];
uint32_t task_redistrib[2];
uint32_t vs[9];
uint32_t hs[9];
uint32_t te[5];
uint32_t ds[11];
uint32_t gs[10];
uint32_t sf[4];
uint32_t ms[2];
uint32_t sm[2];
uint32_t sp[9];
uint32_t raster[5];
uint32_t cps[9];
uint32_t ls[3];
uint32_t db[4];
uint32_t wm_ds[4];
uint32_t wm[2];
uint32_t pr[6];
uint32_t sbe[6];
uint32_t sbe_swiz[11];
uint32_t sbe_mesh[2];
uint32_t ps[12];
uint32_t ps_extra[2];
uint32_t ps_extra_dep[2];
uint32_t ps_blend[2];
uint32_t blend_state[2];
uint32_t cc_state[2];
uint32_t tbimr[4];
} packed;
/** Dirty bits of what needs to be reemitted */
BITSET_DECLARE(emit_dirty, ANV_GFX_STATE_MAX);
}; };
enum anv_internal_kernel_name { enum anv_internal_kernel_name {
@ -2768,28 +2821,6 @@ _anv_combine_address(struct anv_batch *batch, void *location,
_dst = NULL; \ _dst = NULL; \
})) }))
#define anv_batch_emit_merge_protected(batch, cmd, pipeline, state, \
name, protected) \
for (struct cmd name = { 0 }, \
*_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
__builtin_expect(_dst != NULL, 1); \
({ struct anv_gfx_state_ptr *_cmd_state = protected ? \
&(pipeline)->state##_protected : \
&(pipeline)->state; \
uint32_t _partial[__anv_cmd_length(cmd)]; \
assert(_cmd_state->len == __anv_cmd_length(cmd)); \
__anv_cmd_pack(cmd)(batch, _partial, &name); \
for (uint32_t i = 0; i < __anv_cmd_length(cmd); i++) { \
assert((_partial[i] & \
(pipeline)->batch_data[ \
(pipeline)->state.offset + i]) == 0); \
((uint32_t *)_dst)[i] = _partial[i] | \
(pipeline)->batch_data[_cmd_state->offset + i]; \
} \
VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
_dst = NULL; \
}))
#define anv_batch_emit(batch, cmd, name) \ #define anv_batch_emit(batch, cmd, name) \
for (struct cmd name = { __anv_cmd_header(cmd) }, \ for (struct cmd name = { __anv_cmd_header(cmd) }, \
*_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \ *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \

4
src/intel/vulkan/anv_util.c
View file

@ -159,10 +159,8 @@ anv_gfx_state_bit_to_str(enum anv_gfx_state_bits state)
NAME(TASK_CONTROL); NAME(TASK_CONTROL);
NAME(TASK_SHADER); NAME(TASK_SHADER);
NAME(TASK_REDISTRIB); NAME(TASK_REDISTRIB);
NAME(BLEND_STATE_PTR);
NAME(CLIP); NAME(CLIP);
NAME(CC_STATE); NAME(CC_STATE);
NAME(CC_STATE_PTR);
NAME(CPS); NAME(CPS);
NAME(DEPTH_BOUNDS); NAME(DEPTH_BOUNDS);
NAME(INDEX_BUFFER); NAME(INDEX_BUFFER);
@ -180,7 +178,6 @@ anv_gfx_state_bit_to_str(enum anv_gfx_state_bits state)
NAME(VF_TOPOLOGY); NAME(VF_TOPOLOGY);
NAME(VFG); NAME(VFG);
NAME(VIEWPORT_CC); NAME(VIEWPORT_CC);
NAME(VIEWPORT_CC_PTR);
NAME(VIEWPORT_SF_CLIP); NAME(VIEWPORT_SF_CLIP);
NAME(WM); NAME(WM);
NAME(WM_DEPTH_STENCIL); NAME(WM_DEPTH_STENCIL);
@ -190,7 +187,6 @@ anv_gfx_state_bit_to_str(enum anv_gfx_state_bits state)
NAME(TBIMR_TILE_PASS_INFO); NAME(TBIMR_TILE_PASS_INFO);
NAME(FS_MSAA_FLAGS); NAME(FS_MSAA_FLAGS);
NAME(TCS_INPUT_VERTICES); NAME(TCS_INPUT_VERTICES);
NAME(COARSE_STATE);
NAME(MESH_PROVOKING_VERTEX); NAME(MESH_PROVOKING_VERTEX);
default: UNREACHABLE("invalid state"); default: UNREACHABLE("invalid state");
} }

66
src/intel/vulkan/genX_blorp_exec.c
View file

@ -328,7 +328,7 @@ blorp_exec_on_render(struct blorp_batch *batch,
* will trigger a PIPE_CONTROL too. * will trigger a PIPE_CONTROL too.
*/ */
hw_state->ds_write_state = blorp_ds_state; hw_state->ds_write_state = blorp_ds_state;
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_WA_18019816803); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_WA_18019816803);
/* Add the stall that will flush prior to the blorp operation by /* Add the stall that will flush prior to the blorp operation by
* genX(cmd_buffer_apply_pipe_flushes) * genX(cmd_buffer_apply_pipe_flushes)
@ -388,45 +388,45 @@ blorp_exec_on_render(struct blorp_batch *batch,
#endif #endif
/* Flag all the instructions emitted by BLORP. */ /* Flag all the instructions emitted by BLORP. */
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_URB); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_URB);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VF_STATISTICS); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_VF_STATISTICS);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VF); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_VF);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VF_TOPOLOGY); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_VF_TOPOLOGY);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VERTEX_INPUT); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_VERTEX_INPUT);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VF_SGVS); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_VF_SGVS);
#if GFX_VER >= 11 #if GFX_VER >= 11
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VF_SGVS_2); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_VF_SGVS_2);
#endif #endif
#if GFX_VER >= 12 #if GFX_VER >= 12
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_PRIMITIVE_REPLICATION); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_PRIMITIVE_REPLICATION);
#endif #endif
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VIEWPORT_CC_PTR); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_VIEWPORT_CC);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_STREAMOUT); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_STREAMOUT);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_RASTER); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_RASTER);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_CLIP); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_CLIP);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_SAMPLE_MASK); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_SAMPLE_MASK);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_MULTISAMPLE); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_MULTISAMPLE);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_SF); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_SF);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_SBE); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_SBE);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_SBE_SWIZ); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_SBE_SWIZ);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_DEPTH_BOUNDS); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_DEPTH_BOUNDS);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_WM); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_WM);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_WM_DEPTH_STENCIL); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_WM_DEPTH_STENCIL);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VS); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_VS);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_HS); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_HS);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_DS); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_DS);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_TE); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_TE);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_GS); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_GS);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_PS); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_PS);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_PS_EXTRA); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_PS_EXTRA);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_BLEND_STATE_PTR); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_BLEND_STATE);
if (batch->blorp->config.use_mesh_shading) { if (batch->blorp->config.use_mesh_shading) {
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_MESH_CONTROL); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_MESH_CONTROL);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_TASK_CONTROL); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_TASK_CONTROL);
} }
if (params->wm_prog_data) { if (params->wm_prog_data) {
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_CC_STATE_PTR); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_CC_STATE);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_PS_BLEND); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_PS_BLEND);
} }
anv_cmd_dirty_mask_t dirty = ~(ANV_CMD_DIRTY_INDEX_BUFFER | anv_cmd_dirty_mask_t dirty = ~(ANV_CMD_DIRTY_INDEX_BUFFER |

6
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -3688,9 +3688,9 @@ genX(CmdExecuteCommands)(
memset(&container->state.gfx.urb_cfg, 0, sizeof(struct intel_urb_config)); memset(&container->state.gfx.urb_cfg, 0, sizeof(struct intel_urb_config));
/* Reemit all GFX instructions in container */ /* Reemit all GFX instructions in container */
memcpy(container->state.gfx.dyn_state.dirty, BITSET_OR(container->state.gfx.dyn_state.emit_dirty,
device->gfx_dirty_state, container->state.gfx.dyn_state.emit_dirty,
sizeof(container->state.gfx.dyn_state.dirty)); device->gfx_dirty_state);
if (container->device->vk.enabled_extensions.KHR_fragment_shading_rate) { if (container->device->vk.enabled_extensions.KHR_fragment_shading_rate) {
/* Also recompute the CPS_STATE offset */ /* Also recompute the CPS_STATE offset */
struct vk_dynamic_graphics_state *dyn = struct vk_dynamic_graphics_state *dyn =

2
src/intel/vulkan/genX_cmd_draw.c
View file

@ -874,7 +874,7 @@ cmd_buffer_flush_gfx_state(struct anv_cmd_buffer *cmd_buffer)
genX(cmd_buffer_flush_gfx_runtime_state)(cmd_buffer); genX(cmd_buffer_flush_gfx_runtime_state)(cmd_buffer);
/* Flush the HW state into the commmand buffer */ /* Flush the HW state into the commmand buffer */
if (!BITSET_IS_EMPTY(cmd_buffer->state.gfx.dyn_state.dirty)) if (!BITSET_IS_EMPTY(cmd_buffer->state.gfx.dyn_state.emit_dirty))
genX(cmd_buffer_flush_gfx_hw_state)(cmd_buffer); genX(cmd_buffer_flush_gfx_hw_state)(cmd_buffer);
/* If the pipeline changed, we may need to re-allocate push constant space /* If the pipeline changed, we may need to re-allocate push constant space

1702
src/intel/vulkan/genX_gfx_state.c
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File diff suppressed because it is too large Load diff

44
src/intel/vulkan/genX_gpu_memcpy.c
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@ -333,33 +333,33 @@ genX(emit_so_memcpy_fini)(struct anv_memcpy_state *state)
genX(cmd_buffer_ensure_wa_14018283232)(state->cmd_buffer, false); genX(cmd_buffer_ensure_wa_14018283232)(state->cmd_buffer, false);
#endif #endif
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_URB); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_URB);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VF_STATISTICS); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_VF_STATISTICS);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VF); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_VF);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VF_TOPOLOGY); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_VF_TOPOLOGY);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VERTEX_INPUT); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_VERTEX_INPUT);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VF_SGVS); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_VF_SGVS);
#if GFX_VER >= 11 #if GFX_VER >= 11
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VF_SGVS_2); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_VF_SGVS_2);
#endif #endif
#if GFX_VER >= 12 #if GFX_VER >= 12
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_PRIMITIVE_REPLICATION); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_PRIMITIVE_REPLICATION);
#endif #endif
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_SO_DECL_LIST); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_SO_DECL_LIST);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_STREAMOUT); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_STREAMOUT);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_SAMPLE_MASK); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_SAMPLE_MASK);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_MULTISAMPLE); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_MULTISAMPLE);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_SF); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_SF);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_SBE); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_SBE);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VS); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_VS);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_HS); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_HS);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_DS); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_DS);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_TE); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_TE);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_GS); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_GS);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_PS); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_PS);
if (state->cmd_buffer->device->vk.enabled_extensions.EXT_mesh_shader) { if (state->cmd_buffer->device->vk.enabled_extensions.EXT_mesh_shader) {
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_MESH_CONTROL); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_MESH_CONTROL);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_TASK_CONTROL); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_TASK_CONTROL);
} }
state->cmd_buffer->state.gfx.dirty |= state->cmd_buffer->state.gfx.dirty |=

58
src/intel/vulkan/genX_simple_shader.c
View file

@ -346,40 +346,40 @@ genX(emit_simpler_shader_init_fragment)(struct anv_simple_shader *state)
struct anv_gfx_dynamic_state *hw_state = struct anv_gfx_dynamic_state *hw_state =
&state->cmd_buffer->state.gfx.dyn_state; &state->cmd_buffer->state.gfx.dyn_state;
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_URB); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_URB);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VF_STATISTICS); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_VF_STATISTICS);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VF); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_VF);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VF_TOPOLOGY); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_VF_TOPOLOGY);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VERTEX_INPUT); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_VERTEX_INPUT);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VF_SGVS); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_VF_SGVS);
#if GFX_VER >= 11 #if GFX_VER >= 11
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VF_SGVS_2); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_VF_SGVS_2);
#endif #endif
#if GFX_VER >= 12 #if GFX_VER >= 12
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_PRIMITIVE_REPLICATION); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_PRIMITIVE_REPLICATION);
#endif #endif
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_STREAMOUT); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_STREAMOUT);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VIEWPORT_CC); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_VIEWPORT_CC);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_CLIP); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_CLIP);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_RASTER); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_RASTER);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_SAMPLE_MASK); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_SAMPLE_MASK);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_MULTISAMPLE); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_MULTISAMPLE);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_DEPTH_BOUNDS); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_DEPTH_BOUNDS);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_WM); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_WM);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_WM_DEPTH_STENCIL); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_WM_DEPTH_STENCIL);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_SF); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_SF);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_SBE); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_SBE);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VS); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_VS);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_HS); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_HS);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_DS); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_DS);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_TE); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_TE);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_GS); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_GS);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_PS); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_PS);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_PS_EXTRA); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_PS_EXTRA);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_PS_BLEND); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_PS_BLEND);
if (device->vk.enabled_extensions.EXT_mesh_shader) { if (device->vk.enabled_extensions.EXT_mesh_shader) {
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_MESH_CONTROL); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_MESH_CONTROL);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_TASK_CONTROL); BITSET_SET(hw_state->emit_dirty, ANV_GFX_STATE_TASK_CONTROL);
} }
/* Update urb config after simple shader. */ /* Update urb config after simple shader. */