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ac: add has_dcc_constant_encode to ac_gpu_info

Browse source 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
This commit is contained in:
Samuel Pitoiset 2019-08-02 12:16:54 +02:00
parent c08401f035
commit 44a46c09de
9 changed files with 8 additions and 14 deletions
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4
src/amd/common/ac_gpu_info.c
View file

@ -450,6 +450,10 @@ bool ac_query_gpu_info(int fd, void *dev_p,
info->has_distributed_tess = info->chip_class >= GFX8 &&
info->max_se >= 2;
info->has_dcc_constant_encode = info->family == CHIP_RAVEN2 ||
info->family == CHIP_RENOIR ||
info->chip_class >= GFX10;
/* Get the number of good compute units. */
info->num_good_compute_units = 0;
for (i = 0; i < info->max_se; i++)

1
src/amd/common/ac_gpu_info.h
View file

@ -60,6 +60,7 @@ struct radeon_info {
uint32_t tcc_cache_line_size;
bool has_clear_state;
bool has_distributed_tess;
bool has_dcc_constant_encode;
/* There are 2 display DCC codepaths, because display expects unaligned DCC. */
/* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */

2
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -2005,7 +2005,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
bool disable_constant_encode =
cmd_buffer->device->physical_device->has_dcc_constant_encode;
cmd_buffer->device->physical_device->rad_info.has_dcc_constant_encode;
enum chip_class chip_class =
cmd_buffer->device->physical_device->rad_info.chip_class;
uint8_t watermark = chip_class >= GFX10 ? 6 : 4;

4
src/amd/vulkan/radv_device.c
View file

@ -386,10 +386,6 @@ radv_physical_device_init(struct radv_physical_device *device,
(device->rad_info.chip_class >= GFX8 &&
device->rad_info.me_fw_feature >= 41);
device->has_dcc_constant_encode = device->rad_info.family == CHIP_RAVEN2 ||
device->rad_info.family == CHIP_RENOIR ||
device->rad_info.chip_class >= GFX10;
device->use_shader_ballot = device->rad_info.chip_class >= GFX8 &&
device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT;

3
src/amd/vulkan/radv_private.h
View file

@ -298,9 +298,6 @@ struct radv_physical_device {
/* Whether to enable the AMD_shader_ballot extension */
bool use_shader_ballot;
/* Whether DISABLE_CONSTANT_ENCODE_REG is supported. */
bool has_dcc_constant_encode;
/* Number of threads per wave. */
uint8_t ps_wave_size;
uint8_t cs_wave_size;

2
src/gallium/drivers/radeonsi/si_clear.c
View file

@ -559,7 +559,7 @@ static void si_do_fast_color_clear(struct si_context *sctx,
/* Chips with DCC constant encoding don't need to set the clear
* color registers for DCC clear values 0 and 1.
*/
if (sctx->screen->has_dcc_constant_encode && !eliminate_needed)
if (sctx->screen->info.has_dcc_constant_encode && !eliminate_needed)
continue;
if (si_set_clear_color(tex, fb->cbufs[i]->format, color)) {

3
src/gallium/drivers/radeonsi/si_pipe.c
View file

@ -1144,9 +1144,6 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws,
sscreen->info.family == CHIP_RAVEN;
sscreen->has_ls_vgpr_init_bug = sscreen->info.family == CHIP_VEGA10 ||
sscreen->info.family == CHIP_RAVEN;
sscreen->has_dcc_constant_encode = sscreen->info.family == CHIP_RAVEN2 ||
sscreen->info.family == CHIP_RENOIR ||
sscreen->info.chip_class >= GFX10;
sscreen->use_ngg = sscreen->info.chip_class >= GFX10;
sscreen->use_ngg_streamout = sscreen->info.chip_class >= GFX10;

1
src/gallium/drivers/radeonsi/si_pipe.h
View file

@ -498,7 +498,6 @@ struct si_screen {
bool has_gfx9_scissor_bug;
bool has_msaa_sample_loc_bug;
bool has_ls_vgpr_init_bug;
bool has_dcc_constant_encode;
bool dpbb_allowed;
bool dfsm_allowed;
bool llvm_has_working_vgpr_indexing;

2
src/gallium/drivers/radeonsi/si_state.c
View file

@ -127,7 +127,7 @@ static void si_emit_cb_render_state(struct si_context *sctx)
S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(sctx->chip_class <= GFX9) |
S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable) |
S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx->screen->has_dcc_constant_encode));
S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx->screen->info.has_dcc_constant_encode));
}
/* RB+ register settings. */