mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
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i965/fs: Remove dead IR construction code from the visitor.
Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Francisco Jerez
parent
51948085a2
commit
44928b799a
4 changed files with 0 additions and 439 deletions
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@ -214,143 +214,6 @@ fs_inst::resize_sources(uint8_t num_sources)
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}
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}
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#define ALU1(op) \
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fs_inst * \
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fs_visitor::op(const fs_reg &dst, const fs_reg &src0) \
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{ \
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return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0); \
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}
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#define ALU2(op) \
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fs_inst * \
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fs_visitor::op(const fs_reg &dst, const fs_reg &src0, \
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const fs_reg &src1) \
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{ \
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return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1); \
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}
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#define ALU2_ACC(op) \
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fs_inst * \
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fs_visitor::op(const fs_reg &dst, const fs_reg &src0, \
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const fs_reg &src1) \
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{ \
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fs_inst *inst = new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1);\
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inst->writes_accumulator = true; \
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return inst; \
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}
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#define ALU3(op) \
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fs_inst * \
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fs_visitor::op(const fs_reg &dst, const fs_reg &src0, \
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const fs_reg &src1, const fs_reg &src2) \
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{ \
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return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1, src2);\
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}
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ALU1(NOT)
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ALU1(MOV)
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ALU1(FRC)
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ALU1(RNDD)
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ALU1(RNDE)
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ALU1(RNDZ)
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ALU2(ADD)
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ALU2(MUL)
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ALU2_ACC(MACH)
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ALU2(AND)
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ALU2(OR)
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ALU2(XOR)
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ALU2(SHL)
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ALU2(SHR)
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ALU2(ASR)
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ALU3(LRP)
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ALU1(BFREV)
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ALU3(BFE)
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ALU2(BFI1)
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ALU3(BFI2)
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ALU1(FBH)
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ALU1(FBL)
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ALU1(CBIT)
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ALU3(MAD)
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ALU2_ACC(ADDC)
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ALU2_ACC(SUBB)
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ALU2(SEL)
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ALU2(MAC)
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/** Gen4 predicated IF. */
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fs_inst *
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fs_visitor::IF(enum brw_predicate predicate)
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{
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fs_inst *inst = new(mem_ctx) fs_inst(BRW_OPCODE_IF, dispatch_width);
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inst->predicate = predicate;
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return inst;
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}
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/** Gen6 IF with embedded comparison. */
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fs_inst *
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fs_visitor::IF(const fs_reg &src0, const fs_reg &src1,
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enum brw_conditional_mod condition)
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{
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assert(devinfo->gen == 6);
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fs_inst *inst = new(mem_ctx) fs_inst(BRW_OPCODE_IF, dispatch_width,
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reg_null_d, src0, src1);
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inst->conditional_mod = condition;
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return inst;
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}
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/**
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* CMP: Sets the low bit of the destination channels with the result
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* of the comparison, while the upper bits are undefined, and updates
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* the flag register with the packed 16 bits of the result.
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*/
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fs_inst *
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fs_visitor::CMP(fs_reg dst, fs_reg src0, fs_reg src1,
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enum brw_conditional_mod condition)
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{
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fs_inst *inst;
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/* Take the instruction:
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*
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* CMP null<d> src0<f> src1<f>
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*
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* Original gen4 does type conversion to the destination type before
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* comparison, producing garbage results for floating point comparisons.
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*
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* The destination type doesn't matter on newer generations, so we set the
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* type to match src0 so we can compact the instruction.
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*/
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dst.type = src0.type;
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if (dst.file == HW_REG)
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dst.fixed_hw_reg.type = dst.type;
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resolve_ud_negate(&src0);
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resolve_ud_negate(&src1);
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inst = new(mem_ctx) fs_inst(BRW_OPCODE_CMP, dst, src0, src1);
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inst->conditional_mod = condition;
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return inst;
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}
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fs_inst *
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fs_visitor::LOAD_PAYLOAD(const fs_reg &dst, fs_reg *src, int sources,
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int header_size)
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{
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assert(dst.width % 8 == 0);
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fs_inst *inst = new(mem_ctx) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD, dst.width,
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dst, src, sources);
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inst->header_size = header_size;
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for (int i = 0; i < header_size; i++)
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assert(src[i].file != GRF || src[i].width * type_sz(src[i].type) == 32);
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inst->regs_written = header_size;
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for (int i = header_size; i < sources; ++i)
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assert(src[i].file != GRF || src[i].width == dst.width);
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inst->regs_written += (sources - header_size) * (dst.width / 8);
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return inst;
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}
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void
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fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder &bld,
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const fs_reg &dst,
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@ -862,45 +725,6 @@ fs_visitor::no16(const char *format, ...)
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va_end(va);
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}
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fs_inst *
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fs_visitor::emit(enum opcode opcode)
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{
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return emit(new(mem_ctx) fs_inst(opcode, dispatch_width));
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}
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fs_inst *
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fs_visitor::emit(enum opcode opcode, const fs_reg &dst)
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{
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return emit(new(mem_ctx) fs_inst(opcode, dst));
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}
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fs_inst *
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fs_visitor::emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0)
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{
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return emit(new(mem_ctx) fs_inst(opcode, dst, src0));
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}
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fs_inst *
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fs_visitor::emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
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const fs_reg &src1)
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{
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return emit(new(mem_ctx) fs_inst(opcode, dst, src0, src1));
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}
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fs_inst *
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fs_visitor::emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
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const fs_reg &src1, const fs_reg &src2)
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{
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return emit(new(mem_ctx) fs_inst(opcode, dst, src0, src1, src2));
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}
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fs_inst *
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fs_visitor::emit(enum opcode opcode, const fs_reg &dst,
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fs_reg src[], int sources)
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{
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return emit(new(mem_ctx) fs_inst(opcode, dst, src, sources));
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}
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/**
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* Returns true if the instruction has a flag that means it won't
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* update an entire destination register.
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@ -1053,14 +877,6 @@ fs_visitor::vgrf(const glsl_type *const type)
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brw_type_for_base_type(type), dispatch_width);
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}
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fs_reg
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fs_visitor::vgrf(int num_components)
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{
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int reg_width = dispatch_width / 8;
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return fs_reg(GRF, alloc.allocate(num_components * reg_width),
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BRW_REGISTER_TYPE_F, dispatch_width);
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}
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/** Fixed HW reg constructor. */
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fs_reg::fs_reg(enum register_file file, int reg)
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{
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@ -1487,106 +1303,6 @@ fs_visitor::resolve_source_modifiers(fs_reg *src)
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*src = temp;
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}
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fs_reg
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fs_visitor::fix_math_operand(fs_reg src)
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{
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/* Can't do hstride == 0 args on gen6 math, so expand it out. We
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* might be able to do better by doing execsize = 1 math and then
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* expanding that result out, but we would need to be careful with
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* masking.
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*
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* The hardware ignores source modifiers (negate and abs) on math
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* instructions, so we also move to a temp to set those up.
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*/
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if (devinfo->gen == 6 && src.file != UNIFORM && src.file != IMM &&
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!src.abs && !src.negate)
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return src;
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/* Gen7 relaxes most of the above restrictions, but still can't use IMM
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* operands to math
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*/
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if (devinfo->gen >= 7 && src.file != IMM)
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return src;
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fs_reg expanded = vgrf(glsl_type::float_type);
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expanded.type = src.type;
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emit(BRW_OPCODE_MOV, expanded, src);
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return expanded;
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}
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fs_inst *
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fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src)
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{
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switch (opcode) {
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case SHADER_OPCODE_RCP:
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case SHADER_OPCODE_RSQ:
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case SHADER_OPCODE_SQRT:
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case SHADER_OPCODE_EXP2:
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case SHADER_OPCODE_LOG2:
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case SHADER_OPCODE_SIN:
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case SHADER_OPCODE_COS:
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break;
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default:
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unreachable("not reached: bad math opcode");
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}
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/* Can't do hstride == 0 args to gen6 math, so expand it out. We
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* might be able to do better by doing execsize = 1 math and then
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* expanding that result out, but we would need to be careful with
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* masking.
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*
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* Gen 6 hardware ignores source modifiers (negate and abs) on math
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* instructions, so we also move to a temp to set those up.
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*/
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if (devinfo->gen == 6 || devinfo->gen == 7)
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src = fix_math_operand(src);
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fs_inst *inst = emit(opcode, dst, src);
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if (devinfo->gen < 6) {
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inst->base_mrf = 2;
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inst->mlen = dispatch_width / 8;
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}
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return inst;
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}
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fs_inst *
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fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1)
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{
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int base_mrf = 2;
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fs_inst *inst;
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if (devinfo->gen >= 8) {
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inst = emit(opcode, dst, src0, src1);
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} else if (devinfo->gen >= 6) {
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src0 = fix_math_operand(src0);
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src1 = fix_math_operand(src1);
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inst = emit(opcode, dst, src0, src1);
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} else {
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/* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
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* "Message Payload":
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*
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* "Operand0[7]. For the INT DIV functions, this operand is the
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* denominator."
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* ...
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* "Operand1[7]. For the INT DIV functions, this operand is the
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* numerator."
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*/
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bool is_int_div = opcode != SHADER_OPCODE_POW;
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fs_reg &op0 = is_int_div ? src1 : src0;
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fs_reg &op1 = is_int_div ? src0 : src1;
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emit(MOV(fs_reg(MRF, base_mrf + 1, op1.type, dispatch_width), op1));
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inst = emit(opcode, dst, op0, reg_null_f);
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inst->base_mrf = base_mrf;
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inst->mlen = 2 * dispatch_width / 8;
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}
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return inst;
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}
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void
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fs_visitor::emit_discard_jump()
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{
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@ -70,10 +70,6 @@ namespace brw {
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class fs_visitor : public backend_shader
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{
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public:
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const fs_reg reg_null_f;
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const fs_reg reg_null_d;
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const fs_reg reg_null_ud;
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fs_visitor(struct brw_context *brw,
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void *mem_ctx,
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gl_shader_stage stage,
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@ -86,7 +82,6 @@ public:
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~fs_visitor();
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fs_reg vgrf(const glsl_type *const type);
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fs_reg vgrf(int num_components);
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void import_uniforms(fs_visitor *v);
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void setup_uniform_clipplane_values();
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void compute_clip_distance();
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@ -95,65 +90,11 @@ public:
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void swizzle_result(ir_texture_opcode op, int dest_components,
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fs_reg orig_val, uint32_t sampler);
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fs_inst *emit(fs_inst *inst);
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void emit(exec_list list);
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fs_inst *emit(enum opcode opcode);
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fs_inst *emit(enum opcode opcode, const fs_reg &dst);
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fs_inst *emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0);
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fs_inst *emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
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const fs_reg &src1);
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fs_inst *emit(enum opcode opcode, const fs_reg &dst,
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const fs_reg &src0, const fs_reg &src1, const fs_reg &src2);
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fs_inst *emit(enum opcode opcode, const fs_reg &dst,
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fs_reg src[], int sources);
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fs_inst *MOV(const fs_reg &dst, const fs_reg &src);
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fs_inst *NOT(const fs_reg &dst, const fs_reg &src);
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fs_inst *RNDD(const fs_reg &dst, const fs_reg &src);
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fs_inst *RNDE(const fs_reg &dst, const fs_reg &src);
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fs_inst *RNDZ(const fs_reg &dst, const fs_reg &src);
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fs_inst *FRC(const fs_reg &dst, const fs_reg &src);
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fs_inst *ADD(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
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fs_inst *MUL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
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fs_inst *MACH(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
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fs_inst *MAC(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
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fs_inst *SHL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
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fs_inst *SHR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
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fs_inst *ASR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
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fs_inst *AND(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
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fs_inst *OR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
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fs_inst *XOR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
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fs_inst *IF(enum brw_predicate predicate);
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fs_inst *IF(const fs_reg &src0, const fs_reg &src1,
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enum brw_conditional_mod condition);
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fs_inst *CMP(fs_reg dst, fs_reg src0, fs_reg src1,
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enum brw_conditional_mod condition);
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fs_inst *LRP(const fs_reg &dst, const fs_reg &a, const fs_reg &y,
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const fs_reg &x);
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fs_inst *BFREV(const fs_reg &dst, const fs_reg &value);
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fs_inst *BFE(const fs_reg &dst, const fs_reg &bits, const fs_reg &offset,
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const fs_reg &value);
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fs_inst *BFI1(const fs_reg &dst, const fs_reg &bits, const fs_reg &offset);
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fs_inst *BFI2(const fs_reg &dst, const fs_reg &bfi1_dst,
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const fs_reg &insert, const fs_reg &base);
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fs_inst *FBH(const fs_reg &dst, const fs_reg &value);
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fs_inst *FBL(const fs_reg &dst, const fs_reg &value);
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fs_inst *CBIT(const fs_reg &dst, const fs_reg &value);
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fs_inst *MAD(const fs_reg &dst, const fs_reg &c, const fs_reg &b,
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const fs_reg &a);
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fs_inst *ADDC(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
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fs_inst *SUBB(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
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fs_inst *SEL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
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int type_size(const struct glsl_type *type);
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fs_inst *get_instruction_generating_reg(fs_inst *start,
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fs_inst *end,
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const fs_reg ®);
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fs_inst *LOAD_PAYLOAD(const fs_reg &dst, fs_reg *src, int sources,
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int header_size);
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void VARYING_PULL_CONSTANT_LOAD(const brw::fs_builder &bld,
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const fs_reg &dst,
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const fs_reg &surf_index,
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@ -284,14 +225,7 @@ public:
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fs_reg emit_mcs_fetch(fs_reg coordinate, int components, fs_reg sampler);
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void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
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void resolve_source_modifiers(fs_reg *src);
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fs_reg fix_math_operand(fs_reg src);
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fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0);
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fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0, fs_reg src1);
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fs_inst *emit_lrp(const fs_reg &dst, const fs_reg &x, const fs_reg &y,
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const fs_reg &a);
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void emit_discard_jump();
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/** Copy any live channel from \p src to the first channel of \p dst. */
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void emit_uniformize(const fs_reg &dst, const fs_reg &src);
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bool try_replace_with_sel();
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bool opt_peephole_sel();
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bool opt_peephole_predicated_break();
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@ -354,8 +288,6 @@ public:
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void emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
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fs_reg offset);
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|
||||
void resolve_ud_negate(fs_reg *reg);
|
||||
|
||||
fs_reg get_timestamp(const brw::fs_builder &bld);
|
||||
|
||||
struct brw_reg interp_reg(int location, int channel);
|
||||
|
|
@ -417,11 +349,6 @@ public:
|
|||
fs_reg nir_outputs;
|
||||
fs_reg *nir_system_values;
|
||||
|
||||
/** @{ debug annotation info */
|
||||
const char *current_annotation;
|
||||
const void *base_ir;
|
||||
/** @} */
|
||||
|
||||
bool failed;
|
||||
char *fail_msg;
|
||||
bool simd16_unsupported;
|
||||
|
|
|
|||
|
|
@ -444,7 +444,6 @@ void
|
|||
fs_visitor::nir_emit_instr(nir_instr *instr)
|
||||
{
|
||||
const fs_builder abld = bld.annotate(NULL, instr);
|
||||
this->base_ir = instr;
|
||||
|
||||
switch (instr->type) {
|
||||
case nir_instr_type_alu:
|
||||
|
|
@ -472,8 +471,6 @@ fs_visitor::nir_emit_instr(nir_instr *instr)
|
|||
default:
|
||||
unreachable("unknown instruction type");
|
||||
}
|
||||
|
||||
this->base_ir = NULL;
|
||||
}
|
||||
|
||||
static brw_reg_type
|
||||
|
|
|
|||
|
|
@ -77,44 +77,6 @@ fs_visitor::emit_vs_system_value(int location)
|
|||
return reg;
|
||||
}
|
||||
|
||||
fs_inst *
|
||||
fs_visitor::emit_lrp(const fs_reg &dst, const fs_reg &x, const fs_reg &y,
|
||||
const fs_reg &a)
|
||||
{
|
||||
if (devinfo->gen < 6) {
|
||||
/* We can't use the LRP instruction. Emit x*(1-a) + y*a. */
|
||||
fs_reg y_times_a = vgrf(glsl_type::float_type);
|
||||
fs_reg one_minus_a = vgrf(glsl_type::float_type);
|
||||
fs_reg x_times_one_minus_a = vgrf(glsl_type::float_type);
|
||||
|
||||
emit(MUL(y_times_a, y, a));
|
||||
|
||||
fs_reg negative_a = a;
|
||||
negative_a.negate = !a.negate;
|
||||
emit(ADD(one_minus_a, negative_a, fs_reg(1.0f)));
|
||||
emit(MUL(x_times_one_minus_a, x, one_minus_a));
|
||||
|
||||
return emit(ADD(dst, x_times_one_minus_a, y_times_a));
|
||||
} else {
|
||||
/* The LRP instruction actually does op1 * op0 + op2 * (1 - op0), so
|
||||
* we need to reorder the operands.
|
||||
*/
|
||||
return emit(LRP(dst, a, y, x));
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
fs_visitor::emit_uniformize(const fs_reg &dst, const fs_reg &src)
|
||||
{
|
||||
const fs_reg chan_index = vgrf(glsl_type::uint_type);
|
||||
|
||||
emit(SHADER_OPCODE_FIND_LIVE_CHANNEL, component(chan_index, 0))
|
||||
->force_writemask_all = true;
|
||||
emit(SHADER_OPCODE_BROADCAST, component(dst, 0),
|
||||
src, component(chan_index, 0))
|
||||
->force_writemask_all = true;
|
||||
}
|
||||
|
||||
fs_inst *
|
||||
fs_visitor::emit_texture_gen4(ir_texture_opcode op, fs_reg dst,
|
||||
fs_reg coordinate, int coord_components,
|
||||
|
|
@ -1264,29 +1226,6 @@ fs_visitor::emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
|
|||
inst->mlen = mlen;
|
||||
}
|
||||
|
||||
fs_inst *
|
||||
fs_visitor::emit(fs_inst *inst)
|
||||
{
|
||||
if (dispatch_width == 16 && inst->exec_size == 8)
|
||||
inst->force_uncompressed = true;
|
||||
|
||||
inst->annotation = this->current_annotation;
|
||||
inst->ir = this->base_ir;
|
||||
|
||||
this->instructions.push_tail(inst);
|
||||
|
||||
return inst;
|
||||
}
|
||||
|
||||
void
|
||||
fs_visitor::emit(exec_list list)
|
||||
{
|
||||
foreach_in_list_safe(fs_inst, inst, &list) {
|
||||
inst->exec_node::remove();
|
||||
emit(inst);
|
||||
}
|
||||
}
|
||||
|
||||
/** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
|
||||
void
|
||||
fs_visitor::emit_dummy_fs()
|
||||
|
|
@ -1992,18 +1931,6 @@ fs_visitor::emit_urb_writes()
|
|||
}
|
||||
}
|
||||
|
||||
void
|
||||
fs_visitor::resolve_ud_negate(fs_reg *reg)
|
||||
{
|
||||
if (reg->type != BRW_REGISTER_TYPE_UD ||
|
||||
!reg->negate)
|
||||
return;
|
||||
|
||||
fs_reg temp = vgrf(glsl_type::uint_type);
|
||||
emit(MOV(temp, *reg));
|
||||
*reg = temp;
|
||||
}
|
||||
|
||||
void
|
||||
fs_visitor::emit_cs_terminate()
|
||||
{
|
||||
|
|
@ -2034,9 +1961,6 @@ fs_visitor::fs_visitor(struct brw_context *brw,
|
|||
struct gl_program *prog,
|
||||
unsigned dispatch_width)
|
||||
: backend_shader(brw, shader_prog, prog, prog_data, stage),
|
||||
reg_null_f(retype(brw_null_vec(dispatch_width), BRW_REGISTER_TYPE_F)),
|
||||
reg_null_d(retype(brw_null_vec(dispatch_width), BRW_REGISTER_TYPE_D)),
|
||||
reg_null_ud(retype(brw_null_vec(dispatch_width), BRW_REGISTER_TYPE_UD)),
|
||||
key(key), prog_data(prog_data),
|
||||
dispatch_width(dispatch_width), promoted_constants(0),
|
||||
bld(fs_builder(this, dispatch_width).at_end())
|
||||
|
|
@ -2073,9 +1997,6 @@ fs_visitor::fs_visitor(struct brw_context *brw,
|
|||
this->first_non_payload_grf = 0;
|
||||
this->max_grf = devinfo->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
|
||||
|
||||
this->current_annotation = NULL;
|
||||
this->base_ir = NULL;
|
||||
|
||||
this->virtual_grf_start = NULL;
|
||||
this->virtual_grf_end = NULL;
|
||||
this->live_intervals = NULL;
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue