mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-07 09:18:04 +02:00
Merge branch 'r500test' of git://people.freedesktop.org/~airlied/mesa into r345-cleanup
This commit is contained in:
Alex Deucher
commit
44791e2d78
11 changed files with 3572 additions and 98 deletions
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@ -39,6 +39,7 @@ DRIVER_SOURCES = \
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r300_texstate.c \
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r300_vertprog.c \
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r300_fragprog.c \
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r500_fragprog.c \
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r300_shader.c \
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r300_emit.c \
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r300_swtcl.c \
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@ -242,6 +242,7 @@ void r300EmitState(r300ContextPtr r300)
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#define packet0_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->packet0.count)
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#define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
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#define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count)
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static int check_always(r300ContextPtr r300, struct r300_state_atom *atom)
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{
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@ -262,6 +263,20 @@ static int check_vpu(r300ContextPtr r300, struct r300_state_atom *atom)
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return cnt ? (cnt * 4) + 1 : 0;
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}
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static int check_r500fp(r300ContextPtr r300, struct r300_state_atom *atom)
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{
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int cnt;
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cnt = r500fp_count(atom->cmd);
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return cnt ? (cnt * 6) + 1 : 0;
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}
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static int check_r500fp_const(r300ContextPtr r300, struct r300_state_atom *atom)
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{
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int cnt;
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cnt = r500fp_count(atom->cmd);
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return cnt ? (cnt * 4) + 1 : 0;
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}
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#define ALLOC_STATE( ATOM, CHK, SZ, IDX ) \
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do { \
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r300->hw.ATOM.cmd_size = (SZ); \
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@ -281,10 +296,14 @@ void r300InitCmdBuf(r300ContextPtr r300)
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{
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int size, mtu;
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int has_tcl = 1;
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int is_r500 = 0;
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if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
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has_tcl = 0;
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if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
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is_r500 = 1;
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r300->hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */
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mtu = r300->radeon.glCtx->Const.MaxTextureUnits;
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@ -374,29 +393,47 @@ void r300InitCmdBuf(r300ContextPtr r300)
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r300->hw.su_depth_scale.cmd[0] = cmdpacket0(R300_SU_DEPTH_SCALE, 2);
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ALLOC_STATE(rc, always, R300_RC_CMDSIZE, 0);
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r300->hw.rc.cmd[R300_RC_CMD_0] = cmdpacket0(R300_RS_COUNT, 2);
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ALLOC_STATE(ri, always, R300_RI_CMDSIZE, 0);
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r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(R300_RS_IP_0, 8);
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ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
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r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(R300_RS_INST_0, 1);
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if (is_r500) {
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ALLOC_STATE(ri, always, R500_RI_CMDSIZE, 0);
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r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(R500_RS_IP_0, 16);
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ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
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r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(R500_RS_INST_0, 1);
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} else {
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ALLOC_STATE(ri, always, R300_RI_CMDSIZE, 0);
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r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(R300_RS_IP_0, 8);
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ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
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r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(R300_RS_INST_0, 1);
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}
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ALLOC_STATE(sc_hyperz, always, 3, 0);
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r300->hw.sc_hyperz.cmd[0] = cmdpacket0(R300_SC_HYPERZ, 2);
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ALLOC_STATE(sc_screendoor, always, 2, 0);
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r300->hw.sc_screendoor.cmd[0] = cmdpacket0(R300_SC_SCREENDOOR, 1);
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ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0);
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r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(R300_PFS_CNTL_0, 3);
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r300->hw.fp.cmd[R300_FP_CMD_1] = cmdpacket0(R300_PFS_NODE_0, 4);
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ALLOC_STATE(fpt, variable, R300_FPT_CMDSIZE, 0);
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r300->hw.fpt.cmd[R300_FPT_CMD_0] = cmdpacket0(R300_PFS_TEXI_0, 0);
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ALLOC_STATE(us_out_fmt, always, 6, 0);
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r300->hw.us_out_fmt.cmd[0] = cmdpacket0(R500_US_OUT_FMT, 5);
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ALLOC_STATE(fpi[0], variable, R300_FPI_CMDSIZE, 0);
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r300->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_PFS_INSTR0_0, 1);
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ALLOC_STATE(fpi[1], variable, R300_FPI_CMDSIZE, 1);
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r300->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_PFS_INSTR1_0, 1);
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ALLOC_STATE(fpi[2], variable, R300_FPI_CMDSIZE, 2);
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r300->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_PFS_INSTR2_0, 1);
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ALLOC_STATE(fpi[3], variable, R300_FPI_CMDSIZE, 3);
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r300->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_PFS_INSTR3_0, 1);
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if (is_r500) {
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ALLOC_STATE(r500fp, r500fp, R300_FPI_CMDSIZE, 0);
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r300->hw.r500fp.cmd[R300_FPI_CMD_0] = cmdr500fp(0, 0, 0, 0);
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ALLOC_STATE(r500fp_const, r500fp_const, R300_FPP_CMDSIZE, 0);
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r300->hw.r500fp_const.cmd[R300_FPI_CMD_0] = cmdr500fp(0, 0, 1, 0);
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} else {
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ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0);
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r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(R300_PFS_CNTL_0, 3);
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r300->hw.fp.cmd[R300_FP_CMD_1] = cmdpacket0(R300_PFS_NODE_0, 4);
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ALLOC_STATE(fpt, variable, R300_FPT_CMDSIZE, 0);
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r300->hw.fpt.cmd[R300_FPT_CMD_0] = cmdpacket0(R300_PFS_TEXI_0, 0);
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ALLOC_STATE(fpi[0], variable, R300_FPI_CMDSIZE, 0);
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r300->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_PFS_INSTR0_0, 1);
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ALLOC_STATE(fpi[1], variable, R300_FPI_CMDSIZE, 1);
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r300->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_PFS_INSTR1_0, 1);
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ALLOC_STATE(fpi[2], variable, R300_FPI_CMDSIZE, 2);
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r300->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_PFS_INSTR2_0, 1);
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ALLOC_STATE(fpi[3], variable, R300_FPI_CMDSIZE, 3);
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r300->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_PFS_INSTR3_0, 1);
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ALLOC_STATE(fpp, variable, R300_FPP_CMDSIZE, 0);
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r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(R300_PFS_PARAM_0_X, 0);
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}
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ALLOC_STATE(fogs, always, R300_FOGS_CMDSIZE, 0);
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r300->hw.fogs.cmd[R300_FOGS_CMD_0] = cmdpacket0(FG_FOG_BLEND, 1);
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ALLOC_STATE(fogc, always, R300_FOGC_CMDSIZE, 0);
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@ -405,8 +442,6 @@ void r300InitCmdBuf(r300ContextPtr r300)
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r300->hw.at.cmd[R300_AT_CMD_0] = cmdpacket0(FG_ALPHA_FUNC, 2);
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ALLOC_STATE(fg_depth_src, always, 2, 0);
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r300->hw.fg_depth_src.cmd[0] = cmdpacket0(R300_FG_DEPTH_SRC, 1);
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ALLOC_STATE(fpp, variable, R300_FPP_CMDSIZE, 0);
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r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(R300_PFS_PARAM_0_X, 0);
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ALLOC_STATE(rb3d_cctl, always, 2, 0);
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r300->hw.rb3d_cctl.cmd[0] = cmdpacket0(R300_RB3D_CCTL, 1);
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ALLOC_STATE(bld, always, R300_BLD_CMDSIZE, 0);
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@ -456,10 +491,18 @@ void r300InitCmdBuf(r300ContextPtr r300)
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r300->hw.vps.cmd[R300_VPS_CMD_0] =
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cmdvpu(R300_PVS_UPLOAD_POINTSIZE, 1);
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for (i = 0; i < 6; i++) {
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ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
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r300->hw.vpucp[i].cmd[R300_VPUCP_CMD_0] =
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cmdvpu(R300_PVS_UPLOAD_CLIP_PLANE0+i, 1);
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if (is_r500) {
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for (i = 0; i < 6; i++) {
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ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
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r300->hw.vpucp[i].cmd[R300_VPUCP_CMD_0] =
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cmdvpu(R500_PVS_UPLOAD_CLIP_PLANE0+i, 1);
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}
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} else {
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for (i = 0; i < 6; i++) {
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ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
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r300->hw.vpucp[i].cmd[R300_VPUCP_CMD_0] =
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cmdvpu(R300_PVS_UPLOAD_CLIP_PLANE0+i, 1);
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}
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}
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}
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@ -330,6 +330,8 @@ struct r300_state_atom {
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#define R300_RI_INTERP_7 8
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#define R300_RI_CMDSIZE 9
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#define R500_RI_CMDSIZE 17
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#define R300_RR_CMD_0 0 /* rr is variable size (at least 1) */
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#define R300_RR_INST_0 1
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#define R300_RR_INST_1 2
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@ -487,6 +489,8 @@ struct r300_hw_state {
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struct r300_state_atom fp; /* fragment program cntl + nodes (4600) */
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struct r300_state_atom fpt; /* texi - (4620) */
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struct r300_state_atom us_out_fmt; /* (46A4) */
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struct r300_state_atom r500fp; /* r500 fp instructions */
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struct r300_state_atom r500fp_const; /* r500 fp constants */
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struct r300_state_atom fpi[4]; /* fp instructions (46C0/47C0/48C0/49C0) */
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struct r300_state_atom fogs; /* fog state (4BC0) */
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struct r300_state_atom fogc; /* fog color (4BC8) */
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@ -74,6 +74,20 @@ static inline uint32_t cmdvpu(int addr, int count)
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return cmd.u;
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}
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static inline uint32_t cmdr500fp(int addr, int count, int type, int clamp)
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{
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drm_r300_cmd_header_t cmd;
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cmd.r500fp.cmd_type = R300_CMD_R500FP;
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cmd.r500fp.count = count;
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cmd.r500fp.adrhi_flags = ((unsigned int)addr & 0x100) >> 8;
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cmd.r500fp.adrhi_flags |= type ? R500FP_CONSTANT_TYPE : 0;
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cmd.r500fp.adrhi_flags |= clamp ? R500FP_CONSTANT_CLAMP : 0;
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cmd.r500fp.adrlo = ((unsigned int)addr & 0x00FF);
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return cmd.u;
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}
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static inline uint32_t cmdpacket3(int packet)
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{
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drm_r300_cmd_header_t cmd;
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@ -166,6 +180,19 @@ static inline uint32_t cmdpacify(void)
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cmd[0].i = cmdvpu((dest), _n/4); \
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} while (0);
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#define r500fp_start_fragment(dest, length) \
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do { \
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int _n; \
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_n = (length); \
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cmd = (drm_radeon_cmd_header_t*) \
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r300AllocCmdBuf(rmesa, \
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(_n+1), \
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__FUNCTION__); \
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cmd_reserved = _n+1; \
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cmd_written =1; \
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cmd[0].i = cmdr500fp((dest), _n/6, 0, 0); \
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} while (0);
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#define start_packet3(packet, count) \
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{ \
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int _n; \
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@ -186,10 +186,15 @@ static void r300EmitClearState(GLcontext * ctx)
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int cmd_written = 0;
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drm_radeon_cmd_header_t *cmd = NULL;
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int has_tcl = 1;
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int is_r500 = 0;
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if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
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has_tcl = 0;
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if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
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is_r500 = 1;
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/* FIXME: the values written to R300_VAP_INPUT_ROUTE_0_0 and
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* R300_VAP_INPUT_ROUTE_0_1 are in fact known, however, the values are
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* quite complex; see the functions in r300_emit.c.
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@ -271,49 +276,139 @@ static void r300EmitClearState(GLcontext * ctx)
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e32(((dPriv->w * 6) << R300_POINTSIZE_X_SHIFT) |
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((dPriv->h * 6) << R300_POINTSIZE_Y_SHIFT));
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R300_STATECHANGE(r300, ri);
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reg_start(R300_RS_IP_0, 8);
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for (i = 0; i < 8; ++i) {
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e32(R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3));
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if (!is_r500) {
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R300_STATECHANGE(r300, ri);
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reg_start(R300_RS_IP_0, 8);
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for (i = 0; i < 8; ++i) {
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e32(R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3));
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}
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R300_STATECHANGE(r300, rc);
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/* The second constant is needed to get glxgears display anything .. */
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reg_start(R300_RS_COUNT, 1);
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e32((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN);
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e32(0x0);
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R300_STATECHANGE(r300, rr);
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reg_start(R300_RS_INST_0, 0);
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e32(R300_RS_INST_COL_CN_WRITE);
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} else {
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R300_STATECHANGE(r300, ri);
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reg_start(R500_RS_IP_0, 8);
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for (i = 0; i < 8; ++i) {
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e32((1 << R500_RS_IP_TEX_PTR_T_SHIFT) |
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(2 << R500_RS_IP_TEX_PTR_R_SHIFT) |
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(3 << R500_RS_IP_TEX_PTR_Q_SHIFT) );
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}
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R300_STATECHANGE(r300, rc);
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/* The second constant is needed to get glxgears display anything .. */
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reg_start(R300_RS_COUNT, 1);
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e32((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN);
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e32(0x0);
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R300_STATECHANGE(r300, rr);
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reg_start(R500_RS_INST_0, 0);
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e32(R500_RS_INST_COL_CN_WRITE);
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}
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R300_STATECHANGE(r300, rc);
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/* The second constant is needed to get glxgears display anything .. */
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reg_start(R300_RS_COUNT, 1);
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e32((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN);
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e32(0x0);
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if (!is_r500) {
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R300_STATECHANGE(r300, fp);
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reg_start(R300_PFS_CNTL_0, 2);
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e32(0x0);
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e32(0x0);
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e32(0x0);
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reg_start(R300_PFS_NODE_0, 3);
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e32(0x0);
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e32(0x0);
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e32(0x0);
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e32(R300_PFS_NODE_OUTPUT_COLOR);
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R300_STATECHANGE(r300, rr);
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reg_start(R300_RS_INST_0, 0);
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e32(R300_RS_INST_COL_CN_WRITE);
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R300_STATECHANGE(r300, fpi[0]);
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R300_STATECHANGE(r300, fpi[1]);
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R300_STATECHANGE(r300, fpi[2]);
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R300_STATECHANGE(r300, fpi[3]);
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R300_STATECHANGE(r300, fp);
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reg_start(R300_PFS_CNTL_0, 2);
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e32(0x0);
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e32(0x0);
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e32(0x0);
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reg_start(R300_PFS_NODE_0, 3);
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e32(0x0);
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e32(0x0);
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e32(0x0);
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e32(R300_PFS_NODE_OUTPUT_COLOR);
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reg_start(R300_PFS_INSTR0_0, 0);
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e32(FP_INSTRC(MAD, FP_ARGC(SRC0C_XYZ), FP_ARGC(ONE), FP_ARGC(ZERO)));
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R300_STATECHANGE(r300, fpi[0]);
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R300_STATECHANGE(r300, fpi[1]);
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R300_STATECHANGE(r300, fpi[2]);
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R300_STATECHANGE(r300, fpi[3]);
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reg_start(R300_PFS_INSTR1_0, 0);
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e32(FP_SELC(0, NO, XYZ, FP_TMP(0), 0, 0));
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reg_start(R300_PFS_INSTR0_0, 0);
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e32(FP_INSTRC(MAD, FP_ARGC(SRC0C_XYZ), FP_ARGC(ONE), FP_ARGC(ZERO)));
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reg_start(R300_PFS_INSTR2_0, 0);
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e32(FP_INSTRA(MAD, FP_ARGA(SRC0A), FP_ARGA(ONE), FP_ARGA(ZERO)));
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reg_start(R300_PFS_INSTR1_0, 0);
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e32(FP_SELC(0, NO, XYZ, FP_TMP(0), 0, 0));
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reg_start(R300_PFS_INSTR3_0, 0);
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e32(FP_SELA(0, NO, W, FP_TMP(0), 0, 0));
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} else {
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R300_STATECHANGE(r300, r500fp);
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r500fp_start_fragment(0, 12);
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reg_start(R300_PFS_INSTR2_0, 0);
|
||||
e32(FP_INSTRA(MAD, FP_ARGA(SRC0A), FP_ARGA(ONE), FP_ARGA(ZERO)));
|
||||
e32(0x7808);
|
||||
e32(R500_TEX_ID(0) | R500_TEX_INST_LD | R500_TEX_SEM_ACQUIRE | R500_TEX_IGNORE_UNCOVERED);
|
||||
e32(R500_TEX_SRC_ADDR(0) | R500_TEX_SRC_S_SWIZ_R |
|
||||
R500_TEX_SRC_T_SWIZ_G |
|
||||
R500_TEX_DST_ADDR(0) |
|
||||
R500_TEX_DST_R_SWIZ_R |
|
||||
R500_TEX_DST_G_SWIZ_G |
|
||||
R500_TEX_DST_B_SWIZ_B |
|
||||
R500_TEX_DST_A_SWIZ_A);
|
||||
e32(R500_DX_ADDR(0) |
|
||||
R500_DX_S_SWIZ_R |
|
||||
R500_DX_T_SWIZ_R |
|
||||
R500_DX_R_SWIZ_R |
|
||||
R500_DX_Q_SWIZ_R |
|
||||
R500_DY_ADDR(0) |
|
||||
R500_DY_S_SWIZ_R |
|
||||
R500_DY_T_SWIZ_R |
|
||||
R500_DY_R_SWIZ_R |
|
||||
R500_DY_Q_SWIZ_R);
|
||||
e32(0x0);
|
||||
e32(0x0);
|
||||
|
||||
reg_start(R300_PFS_INSTR3_0, 0);
|
||||
e32(FP_SELA(0, NO, W, FP_TMP(0), 0, 0));
|
||||
e32(R500_INST_TYPE_OUT |
|
||||
R500_INST_TEX_SEM_WAIT |
|
||||
R500_INST_LAST |
|
||||
R500_INST_RGB_OMASK_R |
|
||||
R500_INST_RGB_OMASK_G |
|
||||
R500_INST_RGB_OMASK_B |
|
||||
R500_INST_ALPHA_OMASK);
|
||||
|
||||
e32(R500_RGB_ADDR0(0) |
|
||||
R500_RGB_ADDR1(0) |
|
||||
R500_RGB_ADDR1_CONST |
|
||||
R500_RGB_ADDR2(0) |
|
||||
R500_RGB_ADDR2_CONST |
|
||||
R500_RGB_SRCP_OP_1_MINUS_2RGB0);
|
||||
|
||||
e32(R500_ALPHA_ADDR0(0) |
|
||||
R500_ALPHA_ADDR1(0) |
|
||||
R500_ALPHA_ADDR1_CONST |
|
||||
R500_ALPHA_ADDR2(0) |
|
||||
R500_ALPHA_ADDR2_CONST |
|
||||
R500_ALPHA_SRCP_OP_1_MINUS_2A0);
|
||||
|
||||
e32(R500_ALU_RGB_SEL_A_SRC0 |
|
||||
R500_ALU_RGB_R_SWIZ_A_R |
|
||||
R500_ALU_RGB_G_SWIZ_A_G |
|
||||
R500_ALU_RGB_B_SWIZ_A_B |
|
||||
R500_ALU_RGB_SEL_B_SRC0 |
|
||||
R500_ALU_RGB_R_SWIZ_B_1 |
|
||||
R500_ALU_RGB_B_SWIZ_B_1 |
|
||||
R500_ALU_RGB_G_SWIZ_B_1);
|
||||
|
||||
e32(R500_ALPHA_OP_MAD |
|
||||
R500_ALPHA_SWIZ_A_A |
|
||||
R500_ALPHA_SWIZ_B_1);
|
||||
|
||||
e32(R500_ALU_RGBA_OP_MAD |
|
||||
R500_ALU_RGBA_R_SWIZ_0 |
|
||||
R500_ALU_RGBA_G_SWIZ_0 |
|
||||
R500_ALU_RGBA_B_SWIZ_0 |
|
||||
R500_ALU_RGBA_A_SWIZ_0);
|
||||
}
|
||||
|
||||
if (has_tcl) {
|
||||
R300_STATECHANGE(r300, pvs);
|
||||
|
|
|
|||
|
|
@ -657,7 +657,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
|
|||
/* This table specifies the source location and format for up to 16 texture
|
||||
* addresses (i[0]:i[15]) and four colors (c[0]:c[3])
|
||||
*/
|
||||
#define R500_RS_IP_0 0x4074
|
||||
#define R500_RS_IP_0 0x4074
|
||||
#define R500_RS_IP_1 0x4078
|
||||
#define R500_RS_IP_2 0x407C
|
||||
#define R500_RS_IP_3 0x4080
|
||||
|
|
@ -673,12 +673,12 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
|
|||
#define R500_RS_IP_13 0x40A8
|
||||
#define R500_RS_IP_14 0x40AC
|
||||
#define R500_RS_IP_15 0x40B0
|
||||
#define R500_RS_IP_TEX_PTR_S_SHIFT 0
|
||||
#define R500_RS_IP_TEX_PTR_T_SHIFT 6
|
||||
#define R500_RS_IP_TEX_PTR_R_SHIFT 12
|
||||
#define R500_RS_IP_TEX_PTR_Q_SHIFT 18
|
||||
#define R500_RS_IP_COL_PTR_SHIFT 24
|
||||
#define R500_RS_IP_COL_FMT_SHIFT 27
|
||||
#define R500_RS_IP_TEX_PTR_S_SHIFT 0
|
||||
#define R500_RS_IP_TEX_PTR_T_SHIFT 6
|
||||
#define R500_RS_IP_TEX_PTR_R_SHIFT 12
|
||||
#define R500_RS_IP_TEX_PTR_Q_SHIFT 18
|
||||
#define R500_RS_IP_COL_PTR_SHIFT 24
|
||||
#define R500_RS_IP_COL_FMT_SHIFT 27
|
||||
#define R500_RS_IP_COL_FMT_RGBA (0 << 27)
|
||||
#define R500_RS_IP_COL_FMT_RGB0 (1 << 27)
|
||||
#define R500_RS_IP_COL_FMT_RGB1 (2 << 27)
|
||||
|
|
@ -692,7 +692,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
|
|||
#define R500_RS_IP_COL_FMT_1111 (10 << 27)
|
||||
/* gap */
|
||||
#define R500_RS_IP_OFFSET_DIS (0 << 31)
|
||||
#define R500_RS_IP_OFFSET_EN (1 << 31)
|
||||
#define R500_RS_IP_OFFSET_EN (1 << 31)
|
||||
|
||||
/* gap */
|
||||
|
||||
|
|
@ -1138,10 +1138,10 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
|
|||
# define R300_RS_COL_FMT_111A 8
|
||||
# define R300_RS_COL_FMT_1110 9
|
||||
# define R300_RS_COL_FMT_1111 10
|
||||
# define R300_RS_SEL_S(x) (x << 13)
|
||||
# define R300_RS_SEL_T(x) (x << 16)
|
||||
# define R300_RS_SEL_R(x) (x << 19)
|
||||
# define R300_RS_SEL_Q(x) (x << 22)
|
||||
# define R300_RS_SEL_S(x) (x << 13)
|
||||
# define R300_RS_SEL_T(x) (x << 16)
|
||||
# define R300_RS_SEL_R(x) (x << 19)
|
||||
# define R300_RS_SEL_Q(x) (x << 22)
|
||||
# define R300_RS_SEL_C0 0
|
||||
# define R300_RS_SEL_C1 1
|
||||
# define R300_RS_SEL_C2 2
|
||||
|
|
@ -1151,7 +1151,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
|
|||
|
||||
|
||||
/* */
|
||||
#define R500_RS_INST_0 0x4320
|
||||
#define R500_RS_INST_0 0x4320
|
||||
#define R500_RS_INST_1 0x4324
|
||||
#define R500_RS_INST_2 0x4328
|
||||
#define R500_RS_INST_3 0x432c
|
||||
|
|
@ -2598,6 +2598,479 @@ enum {
|
|||
#define R300_PRIM_NUM_VERTICES_SHIFT 16
|
||||
#define R300_PRIM_NUM_VERTICES_MASK 0xffff
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* The R500 unified shader (US) registers come in banks of 512 each, one
|
||||
* for each instruction slot in the shader. You can't touch them directly.
|
||||
* R500_US_VECTOR_INDEX() sets the base instruction to modify; successive
|
||||
* writes to R500_GA_US_VECTOR_DATA autoincrement the index after the
|
||||
* instruction is fully specified.
|
||||
*/
|
||||
#define R500_US_ALU_ALPHA_INST_0 0xa800
|
||||
# define R500_ALPHA_OP_MAD 0
|
||||
# define R500_ALPHA_OP_DP 1
|
||||
# define R500_ALPHA_OP_MIN 2
|
||||
# define R500_ALPHA_OP_MAX 3
|
||||
/* #define R500_ALPHA_OP_RESERVED 4 */
|
||||
# define R500_ALPHA_OP_CND 5
|
||||
# define R500_ALPHA_OP_CMP 6
|
||||
# define R500_ALPHA_OP_FRC 7
|
||||
# define R500_ALPHA_OP_EX2 8
|
||||
# define R500_ALPHA_OP_LN2 9
|
||||
# define R500_ALPHA_OP_RCP 10
|
||||
# define R500_ALPHA_OP_RSQ 11
|
||||
# define R500_ALPHA_OP_SIN 12
|
||||
# define R500_ALPHA_OP_COS 13
|
||||
# define R500_ALPHA_OP_MDH 14
|
||||
# define R500_ALPHA_OP_MDV 15
|
||||
# define R500_ALPHA_ADDRD(x) (x << 4)
|
||||
# define R500_ALPHA_ADDRD_REL (1 << 11)
|
||||
# define R500_ALPHA_SEL_A_SRC0 (0 << 12)
|
||||
# define R500_ALPHA_SEL_A_SRC1 (1 << 12)
|
||||
# define R500_ALPHA_SEL_A_SRC2 (2 << 12)
|
||||
# define R500_ALPHA_SEL_A_SRCP (3 << 12)
|
||||
# define R500_ALPHA_SWIZ_A_R (0 << 14)
|
||||
# define R500_ALPHA_SWIZ_A_G (1 << 14)
|
||||
# define R500_ALPHA_SWIZ_A_B (2 << 14)
|
||||
# define R500_ALPHA_SWIZ_A_A (3 << 14)
|
||||
# define R500_ALPHA_SWIZ_A_0 (4 << 14)
|
||||
# define R500_ALPHA_SWIZ_A_HALF (5 << 14)
|
||||
# define R500_ALPHA_SWIZ_A_1 (6 << 14)
|
||||
/* #define R500_ALPHA_SWIZ_A_UNUSED (7 << 14) */
|
||||
# define R500_ALPHA_MOD_A_NOP (0 << 17)
|
||||
# define R500_ALPHA_MOD_A_NEG (1 << 17)
|
||||
# define R500_ALPHA_MOD_A_ABS (2 << 17)
|
||||
# define R500_ALPHA_MOD_A_NAB (3 << 17)
|
||||
# define R500_ALPHA_SEL_B_SRC0 (0 << 19)
|
||||
# define R500_ALPHA_SEL_B_SRC1 (1 << 19)
|
||||
# define R500_ALPHA_SEL_B_SRC2 (2 << 19)
|
||||
# define R500_ALPHA_SEL_B_SRCP (3 << 19)
|
||||
# define R500_ALPHA_SWIZ_B_R (0 << 21)
|
||||
# define R500_ALPHA_SWIZ_B_G (1 << 21)
|
||||
# define R500_ALPHA_SWIZ_B_B (2 << 21)
|
||||
# define R500_ALPHA_SWIZ_B_A (3 << 21)
|
||||
# define R500_ALPHA_SWIZ_B_0 (4 << 21)
|
||||
# define R500_ALPHA_SWIZ_B_HALF (5 << 21)
|
||||
# define R500_ALPHA_SWIZ_B_1 (6 << 21)
|
||||
/* #define R500_ALPHA_SWIZ_B_UNUSED (7 << 21) */
|
||||
# define R500_ALPHA_MOD_B_NOP (0 << 24)
|
||||
# define R500_ALPHA_MOD_B_NEG (1 << 24)
|
||||
# define R500_ALPHA_MOD_B_ABS (2 << 24)
|
||||
# define R500_ALPHA_MOD_B_NAB (3 << 24)
|
||||
# define R500_ALPHA_OMOD_IDENTITY (0 << 26)
|
||||
# define R500_ALPHA_OMOD_MUL_2 (1 << 26)
|
||||
# define R500_ALPHA_OMOD_MUL_4 (2 << 26)
|
||||
# define R500_ALPHA_OMOD_MUL_8 (3 << 26)
|
||||
# define R500_ALPHA_OMOD_DIV_2 (4 << 26)
|
||||
# define R500_ALPHA_OMOD_DIV_4 (5 << 26)
|
||||
# define R500_ALPHA_OMOD_DIV_8 (6 << 26)
|
||||
# define R500_ALPHA_OMOD_DISABLE (7 << 26)
|
||||
# define R500_ALPHA_TARGET(x) (x << 29)
|
||||
# define R500_ALPHA_W_OMASK (1 << 31)
|
||||
#define R500_US_ALU_ALPHA_ADDR_0 0x9800
|
||||
# define R500_ALPHA_ADDR0(x) (x << 0)
|
||||
# define R500_ALPHA_ADDR0_CONST (1 << 8)
|
||||
# define R500_ALPHA_ADDR0_REL (1 << 9)
|
||||
# define R500_ALPHA_ADDR1(x) (x << 10)
|
||||
# define R500_ALPHA_ADDR1_CONST (1 << 18)
|
||||
# define R500_ALPHA_ADDR1_REL (1 << 19)
|
||||
# define R500_ALPHA_ADDR2(x) (x << 20)
|
||||
# define R500_ALPHA_ADDR2_CONST (1 << 28)
|
||||
# define R500_ALPHA_ADDR2_REL (1 << 29)
|
||||
# define R500_ALPHA_SRCP_OP_1_MINUS_2A0 (0 << 30)
|
||||
# define R500_ALPHA_SRCP_OP_A1_MINUS_A0 (1 << 30)
|
||||
# define R500_ALPHA_SRCP_OP_A1_PLUS_A0 (2 << 30)
|
||||
# define R500_ALPHA_SRCP_OP_1_MINUS_A0 (3 << 30)
|
||||
#define R500_US_ALU_RGBA_INST_0 0xb000
|
||||
# define R500_ALU_RGBA_OP_MAD (0 << 0)
|
||||
# define R500_ALU_RGBA_OP_DP3 (1 << 0)
|
||||
# define R500_ALU_RGBA_OP_DP4 (2 << 0)
|
||||
# define R500_ALU_RGBA_OP_D2A (3 << 0)
|
||||
# define R500_ALU_RGBA_OP_MIN (4 << 0)
|
||||
# define R500_ALU_RGBA_OP_MAX (5 << 0)
|
||||
/* #define R500_ALU_RGBA_OP_RESERVED (6 << 0) */
|
||||
# define R500_ALU_RGBA_OP_CND (7 << 0)
|
||||
# define R500_ALU_RGBA_OP_CMP (8 << 0)
|
||||
# define R500_ALU_RGBA_OP_FRC (9 << 0)
|
||||
# define R500_ALU_RGBA_OP_SOP (10 << 0)
|
||||
# define R500_ALU_RGBA_OP_MDH (11 << 0)
|
||||
# define R500_ALU_RGBA_OP_MDV (12 << 0)
|
||||
# define R500_ALU_RGBA_ADDRD(x) (x << 4)
|
||||
# define R500_ALU_RGBA_ADDRD_REL (1 << 11)
|
||||
# define R500_ALU_RGBA_SEL_C_SRC0 (0 << 12)
|
||||
# define R500_ALU_RGBA_SEL_C_SRC1 (1 << 12)
|
||||
# define R500_ALU_RGBA_SEL_C_SRC2 (2 << 12)
|
||||
# define R500_ALU_RGBA_SEL_C_SRCP (3 << 12)
|
||||
# define R500_ALU_RGBA_R_SWIZ_R (0 << 14)
|
||||
# define R500_ALU_RGBA_R_SWIZ_G (1 << 14)
|
||||
# define R500_ALU_RGBA_R_SWIZ_B (2 << 14)
|
||||
# define R500_ALU_RGBA_R_SWIZ_A (3 << 14)
|
||||
# define R500_ALU_RGBA_R_SWIZ_0 (4 << 14)
|
||||
# define R500_ALU_RGBA_R_SWIZ_HALF (5 << 14)
|
||||
# define R500_ALU_RGBA_R_SWIZ_1 (6 << 14)
|
||||
/* #define R500_ALU_RGBA_R_SWIZ_UNUSED (7 << 14) */
|
||||
# define R500_ALU_RGBA_G_SWIZ_R (0 << 17)
|
||||
# define R500_ALU_RGBA_G_SWIZ_G (1 << 17)
|
||||
# define R500_ALU_RGBA_G_SWIZ_B (2 << 17)
|
||||
# define R500_ALU_RGBA_G_SWIZ_A (3 << 17)
|
||||
# define R500_ALU_RGBA_G_SWIZ_0 (4 << 17)
|
||||
# define R500_ALU_RGBA_G_SWIZ_HALF (5 << 17)
|
||||
# define R500_ALU_RGBA_G_SWIZ_1 (6 << 17)
|
||||
/* #define R500_ALU_RGBA_G_SWIZ_UNUSED (7 << 17) */
|
||||
# define R500_ALU_RGBA_B_SWIZ_R (0 << 20)
|
||||
# define R500_ALU_RGBA_B_SWIZ_G (1 << 20)
|
||||
# define R500_ALU_RGBA_B_SWIZ_B (2 << 20)
|
||||
# define R500_ALU_RGBA_B_SWIZ_A (3 << 20)
|
||||
# define R500_ALU_RGBA_B_SWIZ_0 (4 << 20)
|
||||
# define R500_ALU_RGBA_B_SWIZ_HALF (5 << 20)
|
||||
# define R500_ALU_RGBA_B_SWIZ_1 (6 << 20)
|
||||
/* #define R500_ALU_RGBA_B_SWIZ_UNUSED (7 << 20) */
|
||||
# define R500_ALU_RGBA_MOD_C_NOP (0 << 23)
|
||||
# define R500_ALU_RGBA_MOD_C_NEG (1 << 23)
|
||||
# define R500_ALU_RGBA_MOD_C_ABS (2 << 23)
|
||||
# define R500_ALU_RGBA_MOD_C_NAB (3 << 23)
|
||||
# define R500_ALU_RGBA_ALPHA_SEL_C_SRC0 (0 << 25)
|
||||
# define R500_ALU_RGBA_ALPHA_SEL_C_SRC1 (1 << 25)
|
||||
# define R500_ALU_RGBA_ALPHA_SEL_C_SRC2 (2 << 25)
|
||||
# define R500_ALU_RGBA_ALPHA_SEL_C_SRCP (3 << 25)
|
||||
# define R500_ALU_RGBA_A_SWIZ_R (0 << 27)
|
||||
# define R500_ALU_RGBA_A_SWIZ_G (1 << 27)
|
||||
# define R500_ALU_RGBA_A_SWIZ_B (2 << 27)
|
||||
# define R500_ALU_RGBA_A_SWIZ_A (3 << 27)
|
||||
# define R500_ALU_RGBA_A_SWIZ_0 (4 << 27)
|
||||
# define R500_ALU_RGBA_A_SWIZ_HALF (5 << 27)
|
||||
# define R500_ALU_RGBA_A_SWIZ_1 (6 << 27)
|
||||
/* #define R500_ALU_RGBA_A_SWIZ_UNUSED (7 << 27) */
|
||||
# define R500_ALU_RGBA_ALPHA_MOD_C_NOP (0 << 30)
|
||||
# define R500_ALU_RGBA_ALPHA_MOD_C_NEG (1 << 30)
|
||||
# define R500_ALU_RGBA_ALPHA_MOD_C_ABS (2 << 30)
|
||||
# define R500_ALU_RGBA_ALPHA_MOD_C_NAB (3 << 30)
|
||||
#define R500_US_ALU_RGB_INST_0 0xa000
|
||||
# define R500_ALU_RGB_SEL_A_SRC0 (0 << 0)
|
||||
# define R500_ALU_RGB_SEL_A_SRC1 (1 << 0)
|
||||
# define R500_ALU_RGB_SEL_A_SRC2 (2 << 0)
|
||||
# define R500_ALU_RGB_SEL_A_SRCP (3 << 0)
|
||||
# define R500_ALU_RGB_R_SWIZ_A_R (0 << 2)
|
||||
# define R500_ALU_RGB_R_SWIZ_A_G (1 << 2)
|
||||
# define R500_ALU_RGB_R_SWIZ_A_B (2 << 2)
|
||||
# define R500_ALU_RGB_R_SWIZ_A_A (3 << 2)
|
||||
# define R500_ALU_RGB_R_SWIZ_A_0 (4 << 2)
|
||||
# define R500_ALU_RGB_R_SWIZ_A_HALF (5 << 2)
|
||||
# define R500_ALU_RGB_R_SWIZ_A_1 (6 << 2)
|
||||
/* #define R500_ALU_RGB_R_SWIZ_A_UNUSED (7 << 2) */
|
||||
# define R500_ALU_RGB_G_SWIZ_A_R (0 << 5)
|
||||
# define R500_ALU_RGB_G_SWIZ_A_G (1 << 5)
|
||||
# define R500_ALU_RGB_G_SWIZ_A_B (2 << 5)
|
||||
# define R500_ALU_RGB_G_SWIZ_A_A (3 << 5)
|
||||
# define R500_ALU_RGB_G_SWIZ_A_0 (4 << 5)
|
||||
# define R500_ALU_RGB_G_SWIZ_A_HALF (5 << 5)
|
||||
# define R500_ALU_RGB_G_SWIZ_A_1 (6 << 5)
|
||||
/* #define R500_ALU_RGB_G_SWIZ_A_UNUSED (7 << 5) */
|
||||
# define R500_ALU_RGB_B_SWIZ_A_R (0 << 8)
|
||||
# define R500_ALU_RGB_B_SWIZ_A_G (1 << 8)
|
||||
# define R500_ALU_RGB_B_SWIZ_A_B (2 << 8)
|
||||
# define R500_ALU_RGB_B_SWIZ_A_A (3 << 8)
|
||||
# define R500_ALU_RGB_B_SWIZ_A_0 (4 << 8)
|
||||
# define R500_ALU_RGB_B_SWIZ_A_HALF (5 << 8)
|
||||
# define R500_ALU_RGB_B_SWIZ_A_1 (6 << 8)
|
||||
/* #define R500_ALU_RGB_B_SWIZ_A_UNUSED (7 << 8) */
|
||||
# define R500_ALU_RGB_MOD_A_NOP (0 << 11)
|
||||
# define R500_ALU_RGB_MOD_A_NEG (1 << 11)
|
||||
# define R500_ALU_RGB_MOD_A_ABS (2 << 11)
|
||||
# define R500_ALU_RGB_MOD_A_NAB (3 << 11)
|
||||
# define R500_ALU_RGB_SEL_B_SRC0 (0 << 13)
|
||||
# define R500_ALU_RGB_SEL_B_SRC1 (1 << 13)
|
||||
# define R500_ALU_RGB_SEL_B_SRC2 (2 << 13)
|
||||
# define R500_ALU_RGB_SEL_B_SRCP (3 << 13)
|
||||
# define R500_ALU_RGB_R_SWIZ_B_R (0 << 15)
|
||||
# define R500_ALU_RGB_R_SWIZ_B_G (1 << 15)
|
||||
# define R500_ALU_RGB_R_SWIZ_B_B (2 << 15)
|
||||
# define R500_ALU_RGB_R_SWIZ_B_A (3 << 15)
|
||||
# define R500_ALU_RGB_R_SWIZ_B_0 (4 << 15)
|
||||
# define R500_ALU_RGB_R_SWIZ_B_HALF (5 << 15)
|
||||
# define R500_ALU_RGB_R_SWIZ_B_1 (6 << 15)
|
||||
/* #define R500_ALU_RGB_R_SWIZ_B_UNUSED (7 << 15) */
|
||||
# define R500_ALU_RGB_G_SWIZ_B_R (0 << 18)
|
||||
# define R500_ALU_RGB_G_SWIZ_B_G (1 << 18)
|
||||
# define R500_ALU_RGB_G_SWIZ_B_B (2 << 18)
|
||||
# define R500_ALU_RGB_G_SWIZ_B_A (3 << 18)
|
||||
# define R500_ALU_RGB_G_SWIZ_B_0 (4 << 18)
|
||||
# define R500_ALU_RGB_G_SWIZ_B_HALF (5 << 18)
|
||||
# define R500_ALU_RGB_G_SWIZ_B_1 (6 << 18)
|
||||
/* #define R500_ALU_RGB_G_SWIZ_B_UNUSED (7 << 18) */
|
||||
# define R500_ALU_RGB_B_SWIZ_B_R (0 << 21)
|
||||
# define R500_ALU_RGB_B_SWIZ_B_G (1 << 21)
|
||||
# define R500_ALU_RGB_B_SWIZ_B_B (2 << 21)
|
||||
# define R500_ALU_RGB_B_SWIZ_B_A (3 << 21)
|
||||
# define R500_ALU_RGB_B_SWIZ_B_0 (4 << 21)
|
||||
# define R500_ALU_RGB_B_SWIZ_B_HALF (5 << 21)
|
||||
# define R500_ALU_RGB_B_SWIZ_B_1 (6 << 21)
|
||||
/* #define R500_ALU_RGB_B_SWIZ_B_UNUSED (7 << 21) */
|
||||
# define R500_ALU_RGB_MOD_B_NOP (0 << 24)
|
||||
# define R500_ALU_RGB_MOD_B_NEG (1 << 24)
|
||||
# define R500_ALU_RGB_MOD_B_ABS (2 << 24)
|
||||
# define R500_ALU_RGB_MOD_B_NAB (3 << 24)
|
||||
# define R500_ALU_RGB_OMOD_IDENTITY (0 << 26)
|
||||
# define R500_ALU_RGB_OMOD_MUL_2 (1 << 26)
|
||||
# define R500_ALU_RGB_OMOD_MUL_4 (2 << 26)
|
||||
# define R500_ALU_RGB_OMOD_MUL_8 (3 << 26)
|
||||
# define R500_ALU_RGB_OMOD_DIV_2 (4 << 26)
|
||||
# define R500_ALU_RGB_OMOD_DIV_4 (5 << 26)
|
||||
# define R500_ALU_RGB_OMOD_DIV_8 (6 << 26)
|
||||
# define R500_ALU_RGB_OMOD_DISABLE (7 << 26)
|
||||
# define R500_ALU_RGB_TARGET(x) (x << 29)
|
||||
# define R500_ALU_RGB_WMASK (1 << 31)
|
||||
#define R500_US_ALU_RGB_ADDR_0 0x9000
|
||||
# define R500_RGB_ADDR0(x) (x << 0)
|
||||
# define R500_RGB_ADDR0_CONST (1 << 8)
|
||||
# define R500_RGB_ADDR0_REL (1 << 9)
|
||||
# define R500_RGB_ADDR1(x) (x << 10)
|
||||
# define R500_RGB_ADDR1_CONST (1 << 18)
|
||||
# define R500_RGB_ADDR1_REL (1 << 19)
|
||||
# define R500_RGB_ADDR2(x) (x << 20)
|
||||
# define R500_RGB_ADDR2_CONST (1 << 28)
|
||||
# define R500_RGB_ADDR2_REL (1 << 29)
|
||||
# define R500_RGB_SRCP_OP_1_MINUS_2RGB0 (0 << 30)
|
||||
# define R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 (1 << 30)
|
||||
# define R500_RGB_SRCP_OP_RGB1_PLUS_RGB0 (2 << 30)
|
||||
# define R500_RGB_SRCP_OP_1_MINUS_RGB0 (3 << 30)
|
||||
#define R500_US_CMN_INST_0 0xb800
|
||||
# define R500_INST_TYPE_ALU (0 << 0)
|
||||
# define R500_INST_TYPE_OUT (1 << 0)
|
||||
# define R500_INST_TYPE_FC (2 << 0)
|
||||
# define R500_INST_TYPE_TEX (3 << 0)
|
||||
# define R500_INST_TEX_SEM_WAIT (1 << 2)
|
||||
# define R500_INST_RGB_PRED_SEL_NONE (0 << 3)
|
||||
# define R500_INST_RGB_PRED_SEL_RGBA (1 << 3)
|
||||
# define R500_INST_RGB_PRED_SEL_RRRR (2 << 3)
|
||||
# define R500_INST_RGB_PRED_SEL_GGGG (3 << 3)
|
||||
# define R500_INST_RGB_PRED_SEL_BBBB (4 << 3)
|
||||
# define R500_INST_RGB_PRED_SEL_AAAA (5 << 3)
|
||||
# define R500_INST_RGB_PRED_INV (1 << 6)
|
||||
# define R500_INST_WRITE_INACTIVE (1 << 7)
|
||||
# define R500_INST_LAST (1 << 8)
|
||||
# define R500_INST_NOP (1 << 9)
|
||||
# define R500_INST_ALU_WAIT (1 << 10)
|
||||
# define R500_INST_RGB_WMASK_R (1 << 11)
|
||||
# define R500_INST_RGB_WMASK_G (1 << 12)
|
||||
# define R500_INST_RGB_WMASK_B (1 << 13)
|
||||
# define R500_INST_ALPHA_WMASK (1 << 14)
|
||||
# define R500_INST_RGB_OMASK_R (1 << 15)
|
||||
# define R500_INST_RGB_OMASK_G (1 << 16)
|
||||
# define R500_INST_RGB_OMASK_B (1 << 17)
|
||||
# define R500_INST_ALPHA_OMASK (1 << 18)
|
||||
# define R500_INST_RGB_CLAMP (1 << 19)
|
||||
# define R500_INST_ALPHA_CLAMP (1 << 20)
|
||||
# define R500_INST_ALU_RESULT_SEL (1 << 21)
|
||||
# define R500_INST_ALPHA_PRED_INV (1 << 22)
|
||||
# define R500_INST_ALU_RESULT_OP_EQ (0 << 23)
|
||||
# define R500_INST_ALU_RESULT_OP_LT (1 << 23)
|
||||
# define R500_INST_ALU_RESULT_OP_GE (2 << 23)
|
||||
# define R500_INST_ALU_RESULT_OP_NE (3 << 23)
|
||||
# define R500_INST_ALPHA_PRED_SEL_NONE (0 << 25)
|
||||
# define R500_INST_ALPHA_PRED_SEL_RGBA (1 << 25)
|
||||
# define R500_INST_ALPHA_PRED_SEL_RRRR (2 << 25)
|
||||
# define R500_INST_ALPHA_PRED_SEL_GGGG (3 << 25)
|
||||
# define R500_INST_ALPHA_PRED_SEL_BBBB (4 << 25)
|
||||
# define R500_INST_ALPHA_PRED_SEL_AAAA (5 << 25)
|
||||
/* XXX next four are kind of guessed */
|
||||
# define R500_INST_STAT_WE_R (1 << 28)
|
||||
# define R500_INST_STAT_WE_G (1 << 29)
|
||||
# define R500_INST_STAT_WE_B (1 << 30)
|
||||
# define R500_INST_STAT_WE_A (1 << 31)
|
||||
|
||||
/* note that these are 8 bit lengths, despite the offsets, at least for R500 */
|
||||
#define R500_US_CODE_ADDR 0x4630
|
||||
# define R500_US_CODE_START_ADDR(x) (x << 0)
|
||||
# define R500_US_CODE_END_ADDR(x) (x << 16)
|
||||
#define R500_US_CODE_OFFSET 0x4638
|
||||
# define R500_US_CODE_OFFSET_ADDR(x) (x << 0)
|
||||
#define R500_US_CODE_RANGE 0x4634
|
||||
# define R500_US_CODE_RANGE_ADDR(x) (x << 0)
|
||||
# define R500_US_CODE_RANGE_SIZE(x) (x << 16)
|
||||
#define R500_US_CONFIG 0x4600
|
||||
# define R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO (1 << 1)
|
||||
#define R500_US_FC_ADDR_0 0xa000
|
||||
# define R500_FC_BOOL_ADDR(x) (x << 0)
|
||||
# define R500_FC_INT_ADDR(x) (x << 8)
|
||||
# define R500_FC_JUMP_ADDR(x) (x << 16)
|
||||
# define R500_FC_JUMP_GLOBAL (1 << 31)
|
||||
#define R500_US_FC_BOOL_CONST 0x4620
|
||||
# define R500_FC_KBOOL(x) (x)
|
||||
#define R500_US_FC_CTRL 0x4624
|
||||
# define R500_FC_TEST_EN (1 << 30)
|
||||
# define R500_FC_FULL_FC_EN (1 << 31)
|
||||
#define R500_US_FC_INST_0 0x9800
|
||||
# define R500_FC_OP_JUMP (0 << 0)
|
||||
# define R500_FC_OP_LOOP (1 << 0)
|
||||
# define R500_FC_OP_ENDLOOP (2 << 0)
|
||||
# define R500_FC_OP_REP (3 << 0)
|
||||
# define R500_FC_OP_ENDREP (4 << 0)
|
||||
# define R500_FC_OP_BREAKLOOP (5 << 0)
|
||||
# define R500_FC_OP_BREAKREP (6 << 0)
|
||||
# define R500_FC_OP_CONTINUE (7 << 0)
|
||||
# define R500_FC_B_ELSE (1 << 4)
|
||||
# define R500_FC_JUMP_ANY (1 << 5)
|
||||
# define R500_FC_A_OP_NONE (0 << 6)
|
||||
# define R500_FC_A_OP_POP (1 << 6)
|
||||
# define R500_FC_A_OP_PUSH (2 << 6)
|
||||
# define R500_FC_JUMP_FUNC(x) (x << 8)
|
||||
# define R500_FC_B_POP_CNT(x) (x << 16)
|
||||
# define R500_FC_B_OP0_NONE (0 << 24)
|
||||
# define R500_FC_B_OP0_DECR (1 << 24)
|
||||
# define R500_FC_B_OP0_INCR (2 << 24)
|
||||
# define R500_FC_B_OP1_DECR (0 << 26)
|
||||
# define R500_FC_B_OP1_NONE (1 << 26)
|
||||
# define R500_FC_B_OP1_INCR (2 << 26)
|
||||
# define R500_FC_IGNORE_UNCOVERED (1 << 28)
|
||||
#define R500_US_FC_INT_CONST_0 0x4c00
|
||||
# define R500_FC_INT_CONST_KR(x) (x << 0)
|
||||
# define R500_FC_INT_CONST_KG(x) (x << 8)
|
||||
# define R500_FC_INT_CONST_KB(x) (x << 16)
|
||||
/* _0 through _15 */
|
||||
#define R500_US_FORMAT0_0 0x4640
|
||||
# define R500_FORMAT_TXWIDTH(x) (x << 0)
|
||||
# define R500_FORMAT_TXHEIGHT(x) (x << 11)
|
||||
# define R500_FORMAT_TXDEPTH(x) (x << 22)
|
||||
/* _0 through _3 */
|
||||
#define R500_US_OUT_FMT_0 0x46a4
|
||||
# define R500_OUT_FMT_C4_8 (0 << 0)
|
||||
# define R500_OUT_FMT_C4_10 (1 << 0)
|
||||
# define R500_OUT_FMT_C4_10_GAMMA (2 << 0)
|
||||
# define R500_OUT_FMT_C_16 (3 << 0)
|
||||
# define R500_OUT_FMT_C2_16 (4 << 0)
|
||||
# define R500_OUT_FMT_C4_16 (5 << 0)
|
||||
# define R500_OUT_FMT_C_16_MPEG (6 << 0)
|
||||
# define R500_OUT_FMT_C2_16_MPEG (7 << 0)
|
||||
# define R500_OUT_FMT_C2_4 (8 << 0)
|
||||
# define R500_OUT_FMT_C_3_3_2 (9 << 0)
|
||||
# define R500_OUT_FMT_C_6_5_6 (10 << 0)
|
||||
# define R500_OUT_FMT_C_11_11_10 (11 << 0)
|
||||
# define R500_OUT_FMT_C_10_11_11 (12 << 0)
|
||||
# define R500_OUT_FMT_C_2_10_10_10 (13 << 0)
|
||||
/* #define R500_OUT_FMT_RESERVED (14 << 0) */
|
||||
# define R500_OUT_FMT_UNUSED (15 << 0)
|
||||
# define R500_OUT_FMT_C_16_FP (16 << 0)
|
||||
# define R500_OUT_FMT_C2_16_FP (17 << 0)
|
||||
# define R500_OUT_FMT_C4_16_FP (18 << 0)
|
||||
# define R500_OUT_FMT_C_32_FP (19 << 0)
|
||||
# define R500_OUT_FMT_C2_32_FP (20 << 0)
|
||||
# define R500_OUT_FMT_C4_32_FP (21 << 0)
|
||||
# define R500_C0_SEL_A (0 << 8)
|
||||
# define R500_C0_SEL_R (1 << 8)
|
||||
# define R500_C0_SEL_G (2 << 8)
|
||||
# define R500_C0_SEL_B (3 << 8)
|
||||
# define R500_C1_SEL_A (0 << 10)
|
||||
# define R500_C1_SEL_R (1 << 10)
|
||||
# define R500_C1_SEL_G (2 << 10)
|
||||
# define R500_C1_SEL_B (3 << 10)
|
||||
# define R500_C2_SEL_A (0 << 12)
|
||||
# define R500_C2_SEL_R (1 << 12)
|
||||
# define R500_C2_SEL_G (2 << 12)
|
||||
# define R500_C2_SEL_B (3 << 12)
|
||||
# define R500_C3_SEL_A (0 << 14)
|
||||
# define R500_C3_SEL_R (1 << 14)
|
||||
# define R500_C3_SEL_G (2 << 14)
|
||||
# define R500_C3_SEL_B (3 << 14)
|
||||
# define R500_OUT_SIGN(x) (x << 16)
|
||||
# define R500_ROUND_ADJ (1 << 20)
|
||||
#define R500_US_PIXSIZE 0x4604
|
||||
# define R500_PIX_SIZE(x) (x)
|
||||
#define R500_US_TEX_ADDR_0 0x9800
|
||||
# define R500_TEX_SRC_ADDR(x) (x << 0)
|
||||
# define R500_TEX_SRC_ADDR_REL (1 << 7)
|
||||
# define R500_TEX_SRC_S_SWIZ_R (0 << 8)
|
||||
# define R500_TEX_SRC_S_SWIZ_G (1 << 8)
|
||||
# define R500_TEX_SRC_S_SWIZ_B (2 << 8)
|
||||
# define R500_TEX_SRC_S_SWIZ_A (3 << 8)
|
||||
# define R500_TEX_SRC_T_SWIZ_R (0 << 10)
|
||||
# define R500_TEX_SRC_T_SWIZ_G (1 << 10)
|
||||
# define R500_TEX_SRC_T_SWIZ_B (2 << 10)
|
||||
# define R500_TEX_SRC_T_SWIZ_A (3 << 10)
|
||||
# define R500_TEX_SRC_R_SWIZ_R (0 << 12)
|
||||
# define R500_TEX_SRC_R_SWIZ_G (1 << 12)
|
||||
# define R500_TEX_SRC_R_SWIZ_B (2 << 12)
|
||||
# define R500_TEX_SRC_R_SWIZ_A (3 << 12)
|
||||
# define R500_TEX_SRC_Q_SWIZ_R (0 << 14)
|
||||
# define R500_TEX_SRC_Q_SWIZ_G (1 << 14)
|
||||
# define R500_TEX_SRC_Q_SWIZ_B (2 << 14)
|
||||
# define R500_TEX_SRC_Q_SWIZ_A (3 << 14)
|
||||
# define R500_TEX_DST_ADDR(x) (x << 16)
|
||||
# define R500_TEX_DST_ADDR_REL (1 << 23)
|
||||
# define R500_TEX_DST_R_SWIZ_R (0 << 24)
|
||||
# define R500_TEX_DST_R_SWIZ_G (1 << 24)
|
||||
# define R500_TEX_DST_R_SWIZ_B (2 << 24)
|
||||
# define R500_TEX_DST_R_SWIZ_A (3 << 24)
|
||||
# define R500_TEX_DST_G_SWIZ_R (0 << 26)
|
||||
# define R500_TEX_DST_G_SWIZ_G (1 << 26)
|
||||
# define R500_TEX_DST_G_SWIZ_B (2 << 26)
|
||||
# define R500_TEX_DST_G_SWIZ_A (3 << 26)
|
||||
# define R500_TEX_DST_B_SWIZ_R (0 << 28)
|
||||
# define R500_TEX_DST_B_SWIZ_G (1 << 28)
|
||||
# define R500_TEX_DST_B_SWIZ_B (2 << 28)
|
||||
# define R500_TEX_DST_B_SWIZ_A (3 << 28)
|
||||
# define R500_TEX_DST_A_SWIZ_R (0 << 30)
|
||||
# define R500_TEX_DST_A_SWIZ_G (1 << 30)
|
||||
# define R500_TEX_DST_A_SWIZ_B (2 << 30)
|
||||
# define R500_TEX_DST_A_SWIZ_A (3 << 30)
|
||||
#define R500_US_TEX_ADDR_DXDY_0 0xa000
|
||||
# define R500_DX_ADDR(x) (x << 0)
|
||||
# define R500_DX_ADDR_REL (1 << 7)
|
||||
# define R500_DX_S_SWIZ_R (0 << 8)
|
||||
# define R500_DX_S_SWIZ_G (1 << 8)
|
||||
# define R500_DX_S_SWIZ_B (2 << 8)
|
||||
# define R500_DX_S_SWIZ_A (3 << 8)
|
||||
# define R500_DX_T_SWIZ_R (0 << 10)
|
||||
# define R500_DX_T_SWIZ_G (1 << 10)
|
||||
# define R500_DX_T_SWIZ_B (2 << 10)
|
||||
# define R500_DX_T_SWIZ_A (3 << 10)
|
||||
# define R500_DX_R_SWIZ_R (0 << 12)
|
||||
# define R500_DX_R_SWIZ_G (1 << 12)
|
||||
# define R500_DX_R_SWIZ_B (2 << 12)
|
||||
# define R500_DX_R_SWIZ_A (3 << 12)
|
||||
# define R500_DX_Q_SWIZ_R (0 << 14)
|
||||
# define R500_DX_Q_SWIZ_G (1 << 14)
|
||||
# define R500_DX_Q_SWIZ_B (2 << 14)
|
||||
# define R500_DX_Q_SWIZ_A (3 << 14)
|
||||
# define R500_DY_ADDR(x) (x << 16)
|
||||
# define R500_DY_ADDR_REL (1 << 17)
|
||||
# define R500_DY_S_SWIZ_R (0 << 24)
|
||||
# define R500_DY_S_SWIZ_G (1 << 24)
|
||||
# define R500_DY_S_SWIZ_B (2 << 24)
|
||||
# define R500_DY_S_SWIZ_A (3 << 24)
|
||||
# define R500_DY_T_SWIZ_R (0 << 26)
|
||||
# define R500_DY_T_SWIZ_G (1 << 26)
|
||||
# define R500_DY_T_SWIZ_B (2 << 26)
|
||||
# define R500_DY_T_SWIZ_A (3 << 26)
|
||||
# define R500_DY_R_SWIZ_R (0 << 28)
|
||||
# define R500_DY_R_SWIZ_G (1 << 28)
|
||||
# define R500_DY_R_SWIZ_B (2 << 28)
|
||||
# define R500_DY_R_SWIZ_A (3 << 28)
|
||||
# define R500_DY_Q_SWIZ_R (0 << 30)
|
||||
# define R500_DY_Q_SWIZ_G (1 << 30)
|
||||
# define R500_DY_Q_SWIZ_B (2 << 30)
|
||||
# define R500_DY_Q_SWIZ_A (3 << 30)
|
||||
#define R500_US_TEX_INST_0 0x9000
|
||||
# define R500_TEX_ID(x) (x << 16)
|
||||
# define R500_TEX_INST_NOP (0 << 22)
|
||||
# define R500_TEX_INST_LD (1 << 22)
|
||||
# define R500_TEX_INST_TEXKILL (2 << 22)
|
||||
# define R500_TEX_INST_PROJ (3 << 22)
|
||||
# define R500_TEX_INST_LODBIAS (4 << 22)
|
||||
# define R500_TEX_INST_LOD (5 << 22)
|
||||
# define R500_TEX_INST_DXDY (6 << 22)
|
||||
# define R500_TEX_SEM_ACQUIRE (1 << 25)
|
||||
# define R500_TEX_IGNORE_UNCOVERED (1 << 26)
|
||||
# define R500_TEX_UNSCALED (1 << 27)
|
||||
#define R500_US_W_FMT 0x46b4
|
||||
# define R500_W_FMT_W0 (0 << 0)
|
||||
# define R500_W_FMT_W24 (1 << 0)
|
||||
# define R500_W_FMT_W24FP (2 << 0)
|
||||
# define R500_W_SRC_US (0 << 2)
|
||||
# define R500_W_SRC_RAS (1 << 2)
|
||||
|
||||
|
||||
/* Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR.
|
||||
* Two parameter dwords:
|
||||
* 0. VAP_VTX_FMT: The first parameter is not written to hardware
|
||||
|
|
|
|||
|
|
@ -1436,40 +1436,43 @@ static void r300SetupTextures(GLcontext * ctx)
|
|||
if (!fp) /* should only happenen once, just after context is created */
|
||||
return;
|
||||
|
||||
R300_STATECHANGE(r300, fpt);
|
||||
|
||||
for (i = 0; i < fp->tex.length; i++) {
|
||||
int unit;
|
||||
int opcode;
|
||||
unsigned long val;
|
||||
if (r300->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) {
|
||||
R300_STATECHANGE(r300, fpt);
|
||||
|
||||
unit = fp->tex.inst[i] >> R300_FPITX_IMAGE_SHIFT;
|
||||
unit &= 15;
|
||||
|
||||
val = fp->tex.inst[i];
|
||||
val &= ~R300_FPITX_IMAGE_MASK;
|
||||
|
||||
opcode =
|
||||
(val & R300_FPITX_OPCODE_MASK) >> R300_FPITX_OPCODE_SHIFT;
|
||||
if (opcode == R300_FPITX_OP_KIL) {
|
||||
r300->hw.fpt.cmd[R300_FPT_INSTR_0 + i] = val;
|
||||
} else {
|
||||
if (tmu_mappings[unit] >= 0) {
|
||||
val |=
|
||||
tmu_mappings[unit] <<
|
||||
R300_FPITX_IMAGE_SHIFT;
|
||||
for (i = 0; i < fp->tex.length; i++) {
|
||||
int unit;
|
||||
int opcode;
|
||||
unsigned long val;
|
||||
|
||||
unit = fp->tex.inst[i] >> R300_FPITX_IMAGE_SHIFT;
|
||||
unit &= 15;
|
||||
|
||||
val = fp->tex.inst[i];
|
||||
val &= ~R300_FPITX_IMAGE_MASK;
|
||||
|
||||
opcode =
|
||||
(val & R300_FPITX_OPCODE_MASK) >> R300_FPITX_OPCODE_SHIFT;
|
||||
if (opcode == R300_FPITX_OP_KIL) {
|
||||
r300->hw.fpt.cmd[R300_FPT_INSTR_0 + i] = val;
|
||||
} else {
|
||||
// We get here when the corresponding texture image is incomplete
|
||||
// (e.g. incomplete mipmaps etc.)
|
||||
r300->hw.fpt.cmd[R300_FPT_INSTR_0 + i] = val;
|
||||
if (tmu_mappings[unit] >= 0) {
|
||||
val |=
|
||||
tmu_mappings[unit] <<
|
||||
R300_FPITX_IMAGE_SHIFT;
|
||||
r300->hw.fpt.cmd[R300_FPT_INSTR_0 + i] = val;
|
||||
} else {
|
||||
// We get here when the corresponding texture image is incomplete
|
||||
// (e.g. incomplete mipmaps etc.)
|
||||
r300->hw.fpt.cmd[R300_FPT_INSTR_0 + i] = val;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
r300->hw.fpt.cmd[R300_FPT_CMD_0] =
|
||||
cmdpacket0(R300_PFS_TEXI_0, fp->tex.length);
|
||||
}
|
||||
|
||||
r300->hw.fpt.cmd[R300_FPT_CMD_0] =
|
||||
cmdpacket0(R300_PFS_TEXI_0, fp->tex.length);
|
||||
|
||||
if (RADEON_DEBUG & DEBUG_STATE)
|
||||
fprintf(stderr, "TX_ENABLE: %08x last_hw_tmu=%d\n",
|
||||
r300->hw.txe.cmd[R300_TXE_ENABLE], last_hw_tmu);
|
||||
|
|
@ -1603,6 +1606,136 @@ static void r300SetupRSUnit(GLcontext * ctx)
|
|||
WARN_ONCE("Don't know how to satisfy InputsRead=0x%08x\n", InputsRead);
|
||||
}
|
||||
|
||||
static void r500SetupRSUnit(GLcontext * ctx)
|
||||
{
|
||||
r300ContextPtr r300 = R300_CONTEXT(ctx);
|
||||
/* I'm still unsure if these are needed */
|
||||
GLuint interp_magic[8] = {
|
||||
0x00,
|
||||
1 << 24,
|
||||
2 << 24,
|
||||
3 << 24,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00
|
||||
};
|
||||
union r300_outputs_written OutputsWritten;
|
||||
GLuint InputsRead;
|
||||
int fp_reg, high_rr;
|
||||
int in_texcoords, col_interp_nr;
|
||||
int i;
|
||||
|
||||
if (hw_tcl_on)
|
||||
OutputsWritten.vp_outputs = CURRENT_VERTEX_SHADER(ctx)->key.OutputsWritten;
|
||||
else
|
||||
RENDERINPUTS_COPY(OutputsWritten.index_bitset, r300->state.render_inputs_bitset);
|
||||
|
||||
if (ctx->FragmentProgram._Current)
|
||||
InputsRead = ctx->FragmentProgram._Current->Base.InputsRead;
|
||||
else {
|
||||
fprintf(stderr, "No ctx->FragmentProgram._Current!!\n");
|
||||
return; /* This should only ever happen once.. */
|
||||
}
|
||||
|
||||
R300_STATECHANGE(r300, ri);
|
||||
R300_STATECHANGE(r300, rc);
|
||||
R300_STATECHANGE(r300, rr);
|
||||
|
||||
fp_reg = in_texcoords = col_interp_nr = high_rr = 0;
|
||||
|
||||
r300->hw.rr.cmd[R300_RR_INST_1] = 0;
|
||||
|
||||
if (InputsRead & FRAG_BIT_WPOS) {
|
||||
for (i = 0; i < ctx->Const.MaxTextureUnits; i++)
|
||||
if (!(InputsRead & (FRAG_BIT_TEX0 << i)))
|
||||
break;
|
||||
|
||||
if (i == ctx->Const.MaxTextureUnits) {
|
||||
fprintf(stderr, "\tno free texcoord found...\n");
|
||||
_mesa_exit(-1);
|
||||
}
|
||||
|
||||
InputsRead |= (FRAG_BIT_TEX0 << i);
|
||||
InputsRead &= ~FRAG_BIT_WPOS;
|
||||
}
|
||||
|
||||
for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
|
||||
|
||||
// r300->hw.ri.cmd[R300_RI_INTERP_0 + i] = 0 | R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3) | (in_texcoords << R300_RS_INTERP_SRC_SHIFT)
|
||||
|
||||
r300->hw.ri.cmd[R300_RI_INTERP_0 + i] = (0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
|
||||
(1 << R500_RS_IP_TEX_PTR_T_SHIFT) |
|
||||
(2 << R500_RS_IP_TEX_PTR_R_SHIFT) |
|
||||
(3 << R500_RS_IP_TEX_PTR_Q_SHIFT) |
|
||||
(in_texcoords << 0) | interp_magic[i];
|
||||
|
||||
r300->hw.rr.cmd[R300_RR_INST_0 + fp_reg] = 0;
|
||||
if (InputsRead & (FRAG_BIT_TEX0 << i)) {
|
||||
//assert(r300->state.texture.tc_count != 0);
|
||||
r300->hw.rr.cmd[R300_RR_INST_0 + fp_reg] |= R500_RS_INST_TEX_CN_WRITE | i /* source INTERP */
|
||||
| (fp_reg << R500_RS_INST_TEX_ADDR_SHIFT);
|
||||
high_rr = fp_reg;
|
||||
|
||||
/* Passing invalid data here can lock the GPU. */
|
||||
if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_TEX0 + i, _TNL_ATTRIB_TEX(i))) {
|
||||
InputsRead &= ~(FRAG_BIT_TEX0 << i);
|
||||
fp_reg++;
|
||||
} else {
|
||||
WARN_ONCE("fragprog wants coords for tex%d, vp doesn't provide them!\n", i);
|
||||
}
|
||||
}
|
||||
/* Need to count all coords enabled at vof */
|
||||
if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_TEX0 + i, _TNL_ATTRIB_TEX(i))) {
|
||||
in_texcoords++;
|
||||
}
|
||||
}
|
||||
|
||||
if (InputsRead & FRAG_BIT_COL0) {
|
||||
if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL0, _TNL_ATTRIB_COLOR0)) {
|
||||
// r300->hw.rr.cmd[R300_RR_ROUTE_0] |= 0 | R300_RS_ROUTE_0_COLOR | (fp_reg++ << R300_RS_ROUTE_0_COLOR_DEST_SHIFT);
|
||||
r300->hw.rr.cmd[R300_RR_INST_0] |= 0 | R500_RS_INST_COL_CN_WRITE | (fp_reg++ << R500_RS_INST_COL_ADDR_SHIFT);
|
||||
InputsRead &= ~FRAG_BIT_COL0;
|
||||
col_interp_nr++;
|
||||
} else {
|
||||
WARN_ONCE("fragprog wants col0, vp doesn't provide it\n");
|
||||
}
|
||||
}
|
||||
|
||||
if (InputsRead & FRAG_BIT_COL1) {
|
||||
if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL1, _TNL_ATTRIB_COLOR1)) {
|
||||
// r300->hw.rr.cmd[R300_RR_ROUTE_1] |= R300_RS_ROUTE_1_UNKNOWN11 | R300_RS_ROUTE_1_COLOR1 | (fp_reg++ << R300_RS_ROUTE_1_COLOR1_DEST_SHIFT);
|
||||
r300->hw.rr.cmd[R300_RR_INST_1] |= (1 << 12) | R500_RS_INST_COL_CN_WRITE | (fp_reg++ << R500_RS_INST_COL_ADDR_SHIFT);
|
||||
InputsRead &= ~FRAG_BIT_COL1;
|
||||
if (high_rr < 1)
|
||||
high_rr = 1;
|
||||
col_interp_nr++;
|
||||
} else {
|
||||
WARN_ONCE("fragprog wants col1, vp doesn't provide it\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* Need at least one. This might still lock as the values are undefined... */
|
||||
if (in_texcoords == 0 && col_interp_nr == 0) {
|
||||
r300->hw.rr.cmd[R300_RR_INST_0] |= 0 | R500_RS_INST_COL_CN_WRITE | (fp_reg++ << R500_RS_INST_COL_ADDR_SHIFT);
|
||||
col_interp_nr++;
|
||||
}
|
||||
|
||||
r300->hw.rc.cmd[1] = 0 | ((in_texcoords << 2) << R300_IT_COUNT_SHIFT)
|
||||
| (col_interp_nr << R300_IC_COUNT_SHIFT)
|
||||
| R300_HIRES_EN;
|
||||
|
||||
assert(high_rr >= 0);
|
||||
r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(R300_RS_INST_0, high_rr + 1);
|
||||
r300->hw.rc.cmd[2] = 0xC0 | high_rr;
|
||||
|
||||
if (InputsRead)
|
||||
WARN_ONCE("Don't know how to satisfy InputsRead=0x%08x\n", InputsRead);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
#define bump_vpu_count(ptr, new_count) do{\
|
||||
drm_r300_cmd_header_t* _p=((drm_r300_cmd_header_t*)(ptr));\
|
||||
int _nc=(new_count)/4; \
|
||||
|
|
@ -1913,6 +2046,8 @@ static void r300ResetHwState(r300ContextPtr r300)
|
|||
R300_GB_TILE_PIPE_COUNT_R300;
|
||||
break;
|
||||
case CHIP_FAMILY_R420:
|
||||
case CHIP_FAMILY_RV515:
|
||||
case CHIP_FAMILY_R520:
|
||||
r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] |=
|
||||
R300_GB_TILE_PIPE_COUNT_R420;
|
||||
break;
|
||||
|
|
@ -2163,6 +2298,105 @@ static void r300SetupPixelShader(r300ContextPtr rmesa)
|
|||
}
|
||||
}
|
||||
|
||||
#define bump_r500fp_count(ptr, new_count) do{\
|
||||
drm_r300_cmd_header_t* _p=((drm_r300_cmd_header_t*)(ptr));\
|
||||
int _nc=(new_count)/6; \
|
||||
assert(_nc < 256); \
|
||||
if(_nc>_p->r500fp.count)_p->r500fp.count=_nc;\
|
||||
} while(0)
|
||||
|
||||
#define bump_r500fp_const_count(ptr, new_count) do{\
|
||||
drm_r300_cmd_header_t* _p=((drm_r300_cmd_header_t*)(ptr));\
|
||||
int _nc=(new_count)/4; \
|
||||
assert(_nc < 256); \
|
||||
if(_nc>_p->r500fp.count)_p->r500fp.count=_nc;\
|
||||
} while(0)
|
||||
|
||||
static void r500SetupPixelShader(r300ContextPtr rmesa)
|
||||
{
|
||||
GLcontext *ctx = rmesa->radeon.glCtx;
|
||||
struct r300_fragment_program *fp = (struct r300_fragment_program *)
|
||||
(char *)ctx->FragmentProgram._Current;
|
||||
int i, k;
|
||||
|
||||
if (!fp) /* should only happenen once, just after context is created */
|
||||
return;
|
||||
|
||||
/* emit the standard zero shader */
|
||||
R300_STATECHANGE(rmesa, r500fp);
|
||||
i = 1;
|
||||
rmesa->hw.r500fp.cmd[i++] = 0x7808;
|
||||
rmesa->hw.r500fp.cmd[i++] = R500_TEX_ID(0) | R500_TEX_INST_LD | R500_TEX_SEM_ACQUIRE | R500_TEX_IGNORE_UNCOVERED;
|
||||
rmesa->hw.r500fp.cmd[i++] = R500_TEX_SRC_ADDR(0) | R500_TEX_SRC_S_SWIZ_R |
|
||||
R500_TEX_SRC_T_SWIZ_G |
|
||||
R500_TEX_DST_ADDR(0) |
|
||||
R500_TEX_DST_R_SWIZ_R |
|
||||
R500_TEX_DST_G_SWIZ_G |
|
||||
R500_TEX_DST_B_SWIZ_B |
|
||||
R500_TEX_DST_A_SWIZ_A;
|
||||
rmesa->hw.r500fp.cmd[i++] = R500_DX_ADDR(0) |
|
||||
R500_DX_S_SWIZ_R |
|
||||
R500_DX_T_SWIZ_R |
|
||||
R500_DX_R_SWIZ_R |
|
||||
R500_DX_Q_SWIZ_R |
|
||||
R500_DY_ADDR(0) |
|
||||
R500_DY_S_SWIZ_R |
|
||||
R500_DY_T_SWIZ_R |
|
||||
R500_DY_R_SWIZ_R |
|
||||
R500_DY_Q_SWIZ_R;
|
||||
rmesa->hw.r500fp.cmd[i++] = 0x0;
|
||||
rmesa->hw.r500fp.cmd[i++] = 0x0;
|
||||
|
||||
rmesa->hw.r500fp.cmd[i++] = R500_INST_TYPE_OUT |
|
||||
R500_INST_TEX_SEM_WAIT |
|
||||
R500_INST_LAST |
|
||||
R500_INST_RGB_OMASK_R |
|
||||
R500_INST_RGB_OMASK_G |
|
||||
R500_INST_RGB_OMASK_B |
|
||||
R500_INST_ALPHA_OMASK;
|
||||
|
||||
rmesa->hw.r500fp.cmd[i++] = R500_RGB_ADDR0(0) |
|
||||
R500_RGB_ADDR1(0) |
|
||||
R500_RGB_ADDR1_CONST |
|
||||
R500_RGB_ADDR2(0) |
|
||||
R500_RGB_ADDR2_CONST |
|
||||
R500_RGB_SRCP_OP_1_MINUS_2RGB0;
|
||||
rmesa->hw.r500fp.cmd[i++] = R500_ALPHA_ADDR0(0) |
|
||||
R500_ALPHA_ADDR1(0) |
|
||||
R500_ALPHA_ADDR1_CONST |
|
||||
R500_ALPHA_ADDR2(0) |
|
||||
R500_ALPHA_ADDR2_CONST |
|
||||
R500_ALPHA_SRCP_OP_1_MINUS_2A0;
|
||||
rmesa->hw.r500fp.cmd[i++] = R500_ALU_RGB_SEL_A_SRC0 |
|
||||
R500_ALU_RGB_R_SWIZ_A_R |
|
||||
R500_ALU_RGB_G_SWIZ_A_G |
|
||||
R500_ALU_RGB_B_SWIZ_A_B |
|
||||
R500_ALU_RGB_SEL_B_SRC0 |
|
||||
R500_ALU_RGB_R_SWIZ_B_1 |
|
||||
R500_ALU_RGB_B_SWIZ_B_1 |
|
||||
R500_ALU_RGB_G_SWIZ_B_1;
|
||||
rmesa->hw.r500fp.cmd[i++] = R500_ALPHA_OP_MAD |
|
||||
R500_ALPHA_SWIZ_A_A |
|
||||
R500_ALPHA_SWIZ_B_1;
|
||||
rmesa->hw.r500fp.cmd[i++] = R500_ALU_RGBA_OP_MAD |
|
||||
R500_ALU_RGBA_R_SWIZ_0 |
|
||||
R500_ALU_RGBA_G_SWIZ_0 |
|
||||
R500_ALU_RGBA_B_SWIZ_0 |
|
||||
R500_ALU_RGBA_A_SWIZ_0;
|
||||
|
||||
bump_r500fp_count(rmesa->hw.r500fp.cmd, 12);
|
||||
|
||||
R300_STATECHANGE(rmesa, r500fp_const);
|
||||
for (i = 0; i < fp->const_nr; i++) {
|
||||
rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 0] = r300PackFloat24(fp->constant[i][0]);
|
||||
rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 1] = r300PackFloat24(fp->constant[i][1]);
|
||||
rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 2] = r300PackFloat24(fp->constant[i][2]);
|
||||
rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 3] = r300PackFloat24(fp->constant[i][3]);
|
||||
}
|
||||
bump_r500fp_const_count(rmesa->hw.r500fp_const.cmd, fp->const_nr * 4);
|
||||
|
||||
}
|
||||
|
||||
void r300UpdateShaderStates(r300ContextPtr rmesa)
|
||||
{
|
||||
GLcontext *ctx;
|
||||
|
|
@ -2170,12 +2404,19 @@ void r300UpdateShaderStates(r300ContextPtr rmesa)
|
|||
|
||||
r300UpdateTextureState(ctx);
|
||||
|
||||
r300SetupPixelShader(rmesa);
|
||||
if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
|
||||
r500SetupPixelShader(rmesa);
|
||||
else
|
||||
r300SetupPixelShader(rmesa);
|
||||
r300SetupTextures(ctx);
|
||||
|
||||
if ((rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
|
||||
r300SetupVertexProgram(rmesa);
|
||||
r300SetupRSUnit(ctx);
|
||||
|
||||
if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
|
||||
r500SetupRSUnit(ctx);
|
||||
else
|
||||
r300SetupRSUnit(ctx);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
2476
src/mesa/drivers/dri/r300/r500_fragprog.c
Normal file
2476
src/mesa/drivers/dri/r300/r500_fragprog.c
Normal file
File diff suppressed because it is too large
Load diff
104
src/mesa/drivers/dri/r300/r500_fragprog.h
Normal file
104
src/mesa/drivers/dri/r300/r500_fragprog.h
Normal file
|
|
@ -0,0 +1,104 @@
|
|||
/*
|
||||
* Copyright (C) 2005 Ben Skeggs.
|
||||
*
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish,
|
||||
* distribute, sublicense, and/or sell copies of the Software, and to
|
||||
* permit persons to whom the Software is furnished to do so, subject to
|
||||
* the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the
|
||||
* next paragraph) shall be included in all copies or substantial
|
||||
* portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
|
||||
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
|
||||
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
|
||||
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* Authors:
|
||||
* Ben Skeggs <darktama@iinet.net.au>
|
||||
* Jerome Glisse <j.glisse@gmail.com>
|
||||
*/
|
||||
#ifndef __R300_FRAGPROG_H_
|
||||
#define __R300_FRAGPROG_H_
|
||||
|
||||
#include "glheader.h"
|
||||
#include "macros.h"
|
||||
#include "enums.h"
|
||||
#include "shader/program.h"
|
||||
#include "shader/prog_instruction.h"
|
||||
|
||||
#include "r300_context.h"
|
||||
|
||||
typedef struct r300_fragment_program_swizzle {
|
||||
GLuint length;
|
||||
GLuint src[4];
|
||||
GLuint inst[8];
|
||||
} r300_fragment_program_swizzle_t;
|
||||
|
||||
/* supported hw opcodes */
|
||||
#define PFS_OP_MAD 0
|
||||
#define PFS_OP_DP3 1
|
||||
#define PFS_OP_DP4 2
|
||||
#define PFS_OP_MIN 3
|
||||
#define PFS_OP_MAX 4
|
||||
#define PFS_OP_CMP 5
|
||||
#define PFS_OP_FRC 6
|
||||
#define PFS_OP_EX2 7
|
||||
#define PFS_OP_LG2 8
|
||||
#define PFS_OP_RCP 9
|
||||
#define PFS_OP_RSQ 10
|
||||
#define PFS_OP_REPL_ALPHA 11
|
||||
#define PFS_OP_CMPH 12
|
||||
#define MAX_PFS_OP 12
|
||||
|
||||
#define PFS_FLAG_SAT (1 << 0)
|
||||
#define PFS_FLAG_ABS (1 << 1)
|
||||
|
||||
#define ARG_NEG (1 << 5)
|
||||
#define ARG_ABS (1 << 6)
|
||||
#define ARG_MASK (127 << 0)
|
||||
#define ARG_STRIDE 7
|
||||
#define SRC_CONST (1 << 5)
|
||||
#define SRC_MASK (63 << 0)
|
||||
#define SRC_STRIDE 6
|
||||
|
||||
#define NOP_INST0 ( \
|
||||
(R300_FPI0_OUTC_MAD) | \
|
||||
(R300_FPI0_ARGC_ZERO << R300_FPI0_ARG0C_SHIFT) | \
|
||||
(R300_FPI0_ARGC_ZERO << R300_FPI0_ARG1C_SHIFT) | \
|
||||
(R300_FPI0_ARGC_ZERO << R300_FPI0_ARG2C_SHIFT))
|
||||
#define NOP_INST1 ( \
|
||||
((0 | SRC_CONST) << R300_FPI1_SRC0C_SHIFT) | \
|
||||
((0 | SRC_CONST) << R300_FPI1_SRC1C_SHIFT) | \
|
||||
((0 | SRC_CONST) << R300_FPI1_SRC2C_SHIFT))
|
||||
#define NOP_INST2 ( \
|
||||
(R300_FPI2_OUTA_MAD) | \
|
||||
(R300_FPI2_ARGA_ZERO << R300_FPI2_ARG0A_SHIFT) | \
|
||||
(R300_FPI2_ARGA_ZERO << R300_FPI2_ARG1A_SHIFT) | \
|
||||
(R300_FPI2_ARGA_ZERO << R300_FPI2_ARG2A_SHIFT))
|
||||
#define NOP_INST3 ( \
|
||||
((0 | SRC_CONST) << R300_FPI3_SRC0A_SHIFT) | \
|
||||
((0 | SRC_CONST) << R300_FPI3_SRC1A_SHIFT) | \
|
||||
((0 | SRC_CONST) << R300_FPI3_SRC2A_SHIFT))
|
||||
|
||||
#define DRI_CONF_FP_OPTIMIZATION_SPEED 0
|
||||
#define DRI_CONF_FP_OPTIMIZATION_QUALITY 1
|
||||
|
||||
struct r300_fragment_program;
|
||||
|
||||
extern void r300TranslateFragmentShader(r300ContextPtr r300,
|
||||
struct r300_fragment_program *fp);
|
||||
|
||||
#endif
|
||||
|
|
@ -146,6 +146,9 @@
|
|||
#define PCI_CHIP_RV410_5E4C 0x5E4C
|
||||
#define PCI_CHIP_RV410_5E4D 0x5E4D
|
||||
#define PCI_CHIP_RV410_5E4F 0x5E4F
|
||||
|
||||
#define PCI_CHIP_RV530_71C4 0x71C4
|
||||
|
||||
#define PCI_CHIP_RS350_7834 0x7834
|
||||
#define PCI_CHIP_RS350_7835 0x7835
|
||||
#define PCI_CHIP_RS690_791E 0x791E
|
||||
|
|
@ -169,6 +172,8 @@ enum {
|
|||
CHIP_FAMILY_RV410,
|
||||
CHIP_FAMILY_RS400,
|
||||
CHIP_FAMILY_RS690,
|
||||
CHIP_FAMILY_RV515,
|
||||
CHIP_FAMILY_R520,
|
||||
CHIP_FAMILY_LAST
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -686,6 +686,11 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
|
|||
fprintf(stderr, "Warning, RS690 detected, 3D support is incomplete.\n");
|
||||
break;
|
||||
|
||||
case PCI_CHIP_RV530_71C4:
|
||||
screen->chip_family = CHIP_FAMILY_R520;
|
||||
fprintf(stderr, "Warning, R520 detected, 3D HAHAHAHAHA!!.\n");
|
||||
break;
|
||||
|
||||
default:
|
||||
fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
|
||||
dri_priv->deviceID);
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue