From 446eeccb1c95f65511aa5ffdfd7f6ce23b1ea83f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20=C5=9Alusarz?= Date: Fri, 12 Aug 2022 17:16:17 +0200 Subject: [PATCH] intel/compiler: fix mesh urb write regression Right now even the simplest mesh test (func.mesh.basic.mesh from crucible) fails like this: ASSERT: Scalar MESH validation failed! load_payload(16) vgrf11+0.0:F, vgrf8:D ../../src/intel/compiler/brw_fs_validate.cpp:61: inst->dst.offset / REG_SIZE + regs_written(inst) <= alloc.sizes[inst->dst.nr] Because we try to load 8 regs with LOAD_PAYLOAD in SIMD16 mode. Fixes: 349a040f684 ("intel/fs: Make logical URB write instructions more like other logical instructions") Reviewed-by: Ian Romanick Part-of: --- src/intel/compiler/brw_mesh.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/intel/compiler/brw_mesh.cpp b/src/intel/compiler/brw_mesh.cpp index 52e0ae46818..3c2c63fe51b 100644 --- a/src/intel/compiler/brw_mesh.cpp +++ b/src/intel/compiler/brw_mesh.cpp @@ -911,7 +911,7 @@ emit_urb_direct_writes(const fs_builder &bld, nir_intrinsic_instr *instr, srcs[URB_LOGICAL_SRC_CHANNEL_MASK] = brw_imm_ud(first_mask << 16); srcs[URB_LOGICAL_SRC_DATA] = fs_reg(VGRF, bld.shader->alloc.allocate(length), BRW_REGISTER_TYPE_F); - bld.LOAD_PAYLOAD(srcs[URB_LOGICAL_SRC_DATA], payload_srcs, length, 0); + bld8.LOAD_PAYLOAD(srcs[URB_LOGICAL_SRC_DATA], payload_srcs, length, 0); fs_inst *inst = bld8.emit(SHADER_OPCODE_URB_WRITE_LOGICAL, reg_undef, srcs, ARRAY_SIZE(srcs)); @@ -939,7 +939,7 @@ emit_urb_direct_writes(const fs_builder &bld, nir_intrinsic_instr *instr, srcs[URB_LOGICAL_SRC_CHANNEL_MASK] = brw_imm_ud(second_mask << 16); srcs[URB_LOGICAL_SRC_DATA] = fs_reg(VGRF, bld.shader->alloc.allocate(length), BRW_REGISTER_TYPE_F); - bld.LOAD_PAYLOAD(srcs[URB_LOGICAL_SRC_DATA], payload_srcs, length, 0); + bld8.LOAD_PAYLOAD(srcs[URB_LOGICAL_SRC_DATA], payload_srcs, length, 0); fs_inst *inst = bld8.emit(SHADER_OPCODE_URB_WRITE_LOGICAL, reg_undef, srcs, ARRAY_SIZE(srcs)); @@ -1005,7 +1005,7 @@ emit_urb_indirect_writes(const fs_builder &bld, nir_intrinsic_instr *instr, srcs[URB_LOGICAL_SRC_CHANNEL_MASK] = mask; srcs[URB_LOGICAL_SRC_DATA] = fs_reg(VGRF, bld.shader->alloc.allocate(length), BRW_REGISTER_TYPE_F); - bld.LOAD_PAYLOAD(srcs[URB_LOGICAL_SRC_DATA], payload_srcs, length, 0); + bld8.LOAD_PAYLOAD(srcs[URB_LOGICAL_SRC_DATA], payload_srcs, length, 0); fs_inst *inst = bld8.emit(SHADER_OPCODE_URB_WRITE_LOGICAL, reg_undef, srcs, ARRAY_SIZE(srcs));