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radeon/llvm: Fix lowering of SI_V_CNDLT

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SREG_LIT_0 is a scalar register, so it can only be used in the
first argument of vector instructoins.
This commit is contained in:
Tom Stellard 2012-09-04 11:20:01 -04:00
parent f9fede884b
commit 446d19c12a
1 changed files with 3 additions and 3 deletions
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6
src/gallium/drivers/radeon/SIISelLowering.cpp
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@ -235,10 +235,10 @@ void SITargetLowering::LowerSI_KIL(MachineInstr *MI, MachineBasicBlock &BB,
void SITargetLowering::LowerSI_V_CNDLT(MachineInstr *MI, MachineBasicBlock &BB,
MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const
{
BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CMP_LT_F32_e32),
BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CMP_GT_F32_e32),
AMDGPU::VCC)
.addOperand(MI->getOperand(1))
.addReg(AMDGPU::SREG_LIT_0);
.addReg(AMDGPU::SREG_LIT_0)
.addOperand(MI->getOperand(1));
BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CNDMASK_B32))
.addOperand(MI->getOperand(0))