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amd: unify code for overriding offset and stride for imported buffers
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4863>
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c164ea86e1
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441eaef6a9
4 changed files with 47 additions and 51 deletions
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@ -2189,3 +2189,29 @@ void ac_surface_get_umd_metadata(const struct radeon_info *info,
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*size_metadata += num_mipmap_levels * 4;
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*size_metadata += num_mipmap_levels * 4;
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}
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}
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}
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}
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void ac_surface_override_offset_stride(const struct radeon_info *info,
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struct radeon_surf *surf,
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unsigned num_mipmap_levels,
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uint64_t offset, unsigned pitch)
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{
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if (info->chip_class >= GFX9) {
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if (pitch) {
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surf->u.gfx9.surf_pitch = pitch;
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if (num_mipmap_levels == 1)
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surf->u.gfx9.surf.epitch = pitch - 1;
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surf->u.gfx9.surf_slice_size =
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(uint64_t)pitch * surf->u.gfx9.surf_height * surf->bpe;
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}
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surf->u.gfx9.surf_offset = offset;
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} else {
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surf->u.legacy.level[0].nblk_x = pitch;
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surf->u.legacy.level[0].slice_size_dw =
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((uint64_t)pitch * surf->u.legacy.level[0].nblk_y * surf->bpe) / 4;
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if (offset) {
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for (unsigned i = 0; i < ARRAY_SIZE(surf->u.legacy.level); ++i)
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surf->u.legacy.level[i].offset += offset;
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}
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}
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}
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@ -309,6 +309,11 @@ void ac_surface_get_umd_metadata(const struct radeon_info *info,
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uint32_t desc[8],
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uint32_t desc[8],
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unsigned *size_metadata, uint32_t metadata[64]);
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unsigned *size_metadata, uint32_t metadata[64]);
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void ac_surface_override_offset_stride(const struct radeon_info *info,
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struct radeon_surf *surf,
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unsigned num_mipmap_levels,
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uint64_t offset, unsigned pitch);
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#ifdef __cplusplus
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#ifdef __cplusplus
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}
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}
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#endif
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#endif
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@ -1178,27 +1178,9 @@ radv_image_override_offset_stride(struct radv_device *device,
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struct radv_image *image,
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struct radv_image *image,
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uint64_t offset, uint32_t stride)
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uint64_t offset, uint32_t stride)
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{
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{
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struct radeon_surf *surface = &image->planes[0].surface;
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ac_surface_override_offset_stride(&device->physical_device->rad_info,
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unsigned bpe = vk_format_get_blocksizebits(image->vk_format) / 8;
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&image->planes[0].surface,
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image->info.levels, offset, stride);
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if (device->physical_device->rad_info.chip_class >= GFX9) {
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if (stride) {
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surface->u.gfx9.surf_pitch = stride;
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surface->u.gfx9.surf_slice_size =
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(uint64_t)stride * surface->u.gfx9.surf_height * bpe;
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}
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surface->u.gfx9.surf_offset = offset;
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} else {
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surface->u.legacy.level[0].nblk_x = stride;
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surface->u.legacy.level[0].slice_size_dw =
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((uint64_t)stride * surface->u.legacy.level[0].nblk_y * bpe) / 4;
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if (offset) {
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for (unsigned i = 0; i < ARRAY_SIZE(surface->u.legacy.level); ++i)
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surface->u.legacy.level[i].offset += offset;
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}
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}
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}
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}
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static void
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static void
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@ -209,8 +209,8 @@ static unsigned si_texture_get_offset(struct si_screen *sscreen, struct si_textu
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static int si_init_surface(struct si_screen *sscreen, struct radeon_surf *surface,
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static int si_init_surface(struct si_screen *sscreen, struct radeon_surf *surface,
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const struct pipe_resource *ptex, enum radeon_surf_mode array_mode,
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const struct pipe_resource *ptex, enum radeon_surf_mode array_mode,
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unsigned pitch_in_bytes_override, bool is_imported, bool is_scanout,
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bool is_imported, bool is_scanout, bool is_flushed_depth,
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bool is_flushed_depth, bool tc_compatible_htile)
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bool tc_compatible_htile)
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{
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{
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const struct util_format_description *desc = util_format_description(ptex->format);
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const struct util_format_description *desc = util_format_description(ptex->format);
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bool is_depth, is_stencil;
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bool is_depth, is_stencil;
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@ -311,22 +311,6 @@ static int si_init_surface(struct si_screen *sscreen, struct radeon_surf *surfac
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return r;
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return r;
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}
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}
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unsigned pitch = pitch_in_bytes_override / bpe;
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if (sscreen->info.chip_class >= GFX9) {
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if (pitch) {
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surface->u.gfx9.surf_pitch = pitch;
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if (ptex->last_level == 0)
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surface->u.gfx9.surf.epitch = pitch - 1;
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surface->u.gfx9.surf_slice_size = (uint64_t)pitch * surface->u.gfx9.surf_height * bpe;
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}
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} else {
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if (pitch) {
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surface->u.legacy.level[0].nblk_x = pitch;
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surface->u.legacy.level[0].slice_size_dw =
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((uint64_t)pitch * surface->u.legacy.level[0].nblk_y * bpe) / 4;
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}
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}
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return 0;
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return 0;
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}
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}
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@ -974,7 +958,8 @@ static struct si_texture *si_texture_create_object(struct pipe_screen *screen,
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const struct pipe_resource *base,
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const struct pipe_resource *base,
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const struct radeon_surf *surface,
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const struct radeon_surf *surface,
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const struct si_texture *plane0,
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const struct si_texture *plane0,
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struct pb_buffer *imported_buf, uint64_t offset,
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struct pb_buffer *imported_buf,
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uint64_t offset, unsigned pitch_in_bytes,
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uint64_t alloc_size, unsigned alignment)
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uint64_t alloc_size, unsigned alignment)
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{
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{
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struct si_texture *tex;
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struct si_texture *tex;
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@ -1020,12 +1005,9 @@ static struct si_texture *si_texture_create_object(struct pipe_screen *screen,
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*/
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*/
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tex->ps_draw_ratio = 0;
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tex->ps_draw_ratio = 0;
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if (sscreen->info.chip_class >= GFX9) {
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ac_surface_override_offset_stride(&sscreen->info, &tex->surface,
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tex->surface.u.gfx9.surf_offset = offset;
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tex->buffer.b.b.last_level + 1,
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} else {
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offset, pitch_in_bytes / tex->surface.bpe);
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for (unsigned i = 0; i < ARRAY_SIZE(surface->u.legacy.level); ++i)
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tex->surface.u.legacy.level[i].offset += offset;
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}
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if (tex->is_depth) {
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if (tex->is_depth) {
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if (sscreen->info.chip_class >= GFX9) {
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if (sscreen->info.chip_class >= GFX9) {
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@ -1340,7 +1322,7 @@ struct pipe_resource *si_texture_create(struct pipe_screen *screen,
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if (num_planes > 1)
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if (num_planes > 1)
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plane_templ[i].bind |= PIPE_BIND_SHARED;
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plane_templ[i].bind |= PIPE_BIND_SHARED;
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if (si_init_surface(sscreen, &surface[i], &plane_templ[i], tile_mode, 0, false,
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if (si_init_surface(sscreen, &surface[i], &plane_templ[i], tile_mode, false,
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plane_templ[i].bind & PIPE_BIND_SCANOUT, is_flushed_depth,
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plane_templ[i].bind & PIPE_BIND_SCANOUT, is_flushed_depth,
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tc_compatible_htile))
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tc_compatible_htile))
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return NULL;
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return NULL;
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@ -1355,7 +1337,7 @@ struct pipe_resource *si_texture_create(struct pipe_screen *screen,
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for (unsigned i = 0; i < num_planes; i++) {
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for (unsigned i = 0; i < num_planes; i++) {
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struct si_texture *tex =
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struct si_texture *tex =
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si_texture_create_object(screen, &plane_templ[i], &surface[i], plane0, NULL,
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si_texture_create_object(screen, &plane_templ[i], &surface[i], plane0, NULL,
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plane_offset[i], total_size, max_alignment);
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plane_offset[i], 0, total_size, max_alignment);
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if (!tex) {
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if (!tex) {
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si_texture_reference(&plane0, NULL);
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si_texture_reference(&plane0, NULL);
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return NULL;
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return NULL;
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@ -1378,7 +1360,7 @@ struct pipe_resource *si_texture_create(struct pipe_screen *screen,
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static struct pipe_resource *si_texture_from_winsys_buffer(struct si_screen *sscreen,
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static struct pipe_resource *si_texture_from_winsys_buffer(struct si_screen *sscreen,
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const struct pipe_resource *templ,
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const struct pipe_resource *templ,
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struct pb_buffer *buf, unsigned stride,
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struct pb_buffer *buf, unsigned stride,
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unsigned offset, unsigned usage,
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uint64_t offset, unsigned usage,
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bool dedicated)
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bool dedicated)
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{
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{
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struct radeon_surf surface = {};
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struct radeon_surf surface = {};
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@ -1418,12 +1400,13 @@ static struct pipe_resource *si_texture_from_winsys_buffer(struct si_screen *ssc
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metadata.mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
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metadata.mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
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}
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}
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r = si_init_surface(sscreen, &surface, templ, metadata.mode, stride, true,
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r = si_init_surface(sscreen, &surface, templ, metadata.mode, true,
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surface.flags & RADEON_SURF_SCANOUT, false, false);
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surface.flags & RADEON_SURF_SCANOUT, false, false);
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if (r)
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if (r)
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return NULL;
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return NULL;
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tex = si_texture_create_object(&sscreen->b, templ, &surface, NULL, buf, offset, 0, 0);
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tex = si_texture_create_object(&sscreen->b, templ, &surface, NULL, buf,
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offset, stride, 0, 0);
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if (!tex)
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if (!tex)
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return NULL;
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return NULL;
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