turnip: initialize pipeline->rb_{stencil,depth}_cntl always

This change will simplify further changes on LRZ state management.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8615>
This commit is contained in:
Samuel Iglesias Gonsálvez 2021-02-11 07:53:06 +01:00
parent 1f9fb7677b
commit 43ebba4e88

View file

@ -2683,16 +2683,14 @@ tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
if (tu_pipeline_static_state(pipeline, &cs, TU_DYNAMIC_STATE_RB_DEPTH_CNTL, 2)) {
tu_cs_emit_pkt4(&cs, REG_A6XX_RB_DEPTH_CNTL, 1);
tu_cs_emit(&cs, rb_depth_cntl);
} else {
pipeline->rb_depth_cntl = rb_depth_cntl;
}
pipeline->rb_depth_cntl = rb_depth_cntl;
if (tu_pipeline_static_state(pipeline, &cs, TU_DYNAMIC_STATE_RB_STENCIL_CNTL, 2)) {
tu_cs_emit_pkt4(&cs, REG_A6XX_RB_STENCIL_CONTROL, 1);
tu_cs_emit(&cs, rb_stencil_cntl);
} else {
pipeline->rb_stencil_cntl = rb_stencil_cntl;
}
pipeline->rb_stencil_cntl = rb_stencil_cntl;
/* the remaining draw states arent used if there is no d/s, leave them empty */
if (builder->depth_attachment_format == VK_FORMAT_UNDEFINED)