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r600/sfn: lower bany/ball *(n)equal in nir
The code emitted in the backend was not better and often worse then what we get with the lowering. Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36101>
This commit is contained in:
Gert Wollny
Marge Bot
parent
1123987bb3
commit
43d877ce1a
2 changed files with 0 additions and 184 deletions
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@ -1384,15 +1384,6 @@ emit_alu_op3(const nir_alu_instr& alu,
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Shader& shader,
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const std::array<int, 3>& src_shuffle = {0, 1, 2});
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static bool
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emit_any_all_fcomp2(const nir_alu_instr& alu, EAluOp opcode, Shader& shader);
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static bool
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emit_any_all_fcomp(
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const nir_alu_instr& alu, EAluOp opcode, int nc, bool all, Shader& shader);
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static bool
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emit_any_all_icomp(
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const nir_alu_instr& alu, EAluOp opcode, int nc, bool all, Shader& shader);
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static bool
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emit_alu_comb_with_zero(const nir_alu_instr& alu, EAluOp opcode, Shader& shader);
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static bool
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emit_unpack_64_2x32_split(const nir_alu_instr& alu, int comp, Shader& shader);
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@ -1651,31 +1642,6 @@ AluInstr::from_nir(nir_alu_instr *alu, Shader& shader)
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return emit_alu_op1(*alu, op1_bfrev_int, shader);
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case nir_op_bitfield_select:
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return emit_alu_op3(*alu, op3_bfi_int, shader);
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case nir_op_b32all_fequal2:
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return emit_any_all_fcomp2(*alu, op2_sete_dx10, shader);
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case nir_op_b32all_fequal3:
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return emit_any_all_fcomp(*alu, op2_sete, 3, true, shader);
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case nir_op_b32all_fequal4:
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return emit_any_all_fcomp(*alu, op2_sete, 4, true, shader);
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case nir_op_b32all_iequal2:
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return emit_any_all_icomp(*alu, op2_sete_int, 2, true, shader);
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case nir_op_b32all_iequal3:
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return emit_any_all_icomp(*alu, op2_sete_int, 3, true, shader);
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case nir_op_b32all_iequal4:
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return emit_any_all_icomp(*alu, op2_sete_int, 4, true, shader);
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case nir_op_b32any_fnequal2:
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return emit_any_all_fcomp2(*alu, op2_setne_dx10, shader);
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case nir_op_b32any_fnequal3:
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return emit_any_all_fcomp(*alu, op2_setne, 3, false, shader);
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case nir_op_b32any_fnequal4:
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return emit_any_all_fcomp(*alu, op2_setne, 4, false, shader);
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case nir_op_b32any_inequal2:
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return emit_any_all_icomp(*alu, op2_setne_int, 2, false, shader);
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case nir_op_b32any_inequal3:
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return emit_any_all_icomp(*alu, op2_setne_int, 3, false, shader);
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case nir_op_b32any_inequal4:
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return emit_any_all_icomp(*alu, op2_setne_int, 4, false, shader);
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case nir_op_b32csel:
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return emit_alu_op3(*alu, op3_cnde_int, shader, {0, 2, 1});
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@ -2450,148 +2416,6 @@ emit_alu_op3(const nir_alu_instr& alu,
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return true;
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}
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static bool
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emit_any_all_fcomp2(const nir_alu_instr& alu, EAluOp opcode, Shader& shader)
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{
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AluInstr *ir = nullptr;
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auto& value_factory = shader.value_factory();
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PRegister tmp[2];
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tmp[0] = value_factory.temp_register();
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tmp[1] = value_factory.temp_register();
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for (unsigned i = 0; i < 2; ++i) {
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ir = new AluInstr(opcode,
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tmp[i],
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value_factory.src(alu.src[0], i),
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value_factory.src(alu.src[1], i),
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{alu_write});
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shader.emit_instruction(ir);
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}
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ir->set_alu_flag(alu_last_instr);
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opcode = (opcode == op2_setne_dx10) ? op2_or_int : op2_and_int;
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ir = new AluInstr(opcode,
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value_factory.dest(alu.def, 0, pin_free),
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tmp[0],
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tmp[1],
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AluInstr::last_write);
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shader.emit_instruction(ir);
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return true;
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}
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static bool
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emit_any_all_fcomp(const nir_alu_instr& alu, EAluOp op, int nc, bool all, Shader& shader)
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{
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/* This should probabyl be lowered in nir */
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auto& value_factory = shader.value_factory();
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AluInstr *ir = nullptr;
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RegisterVec4 v = value_factory.temp_vec4(pin_group);
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AluInstr::SrcValues s;
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for (int i = 0; i < nc; ++i) {
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s.push_back(v[i]);
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}
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for (int i = nc; i < 4; ++i)
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s.push_back(value_factory.inline_const(all ? ALU_SRC_1 : ALU_SRC_0, 0));
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for (int i = 0; i < nc; ++i) {
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ir = new AluInstr(op,
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v[i],
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value_factory.src(alu.src[0], i),
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value_factory.src(alu.src[1], i),
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{alu_write});
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shader.emit_instruction(ir);
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}
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if (ir)
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ir->set_alu_flag(alu_last_instr);
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auto max_val = value_factory.temp_register();
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ir = new AluInstr(op1_max4, max_val, s, AluInstr::last_write, 4);
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if (all) {
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ir->set_source_mod(0, AluInstr::mod_neg);
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ir->set_source_mod(1, AluInstr::mod_neg);
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ir->set_source_mod(2, AluInstr::mod_neg);
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ir->set_source_mod(3, AluInstr::mod_neg);
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}
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shader.emit_instruction(ir);
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if (all)
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op = (op == op2_sete) ? op2_sete_dx10 : op2_setne_dx10;
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else
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op = (op == op2_sete) ? op2_setne_dx10 : op2_sete_dx10;
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ir = new AluInstr(op,
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value_factory.dest(alu.def, 0, pin_free),
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max_val,
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value_factory.inline_const(ALU_SRC_1, 0),
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AluInstr::last_write);
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if (all)
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ir->set_source_mod(1, AluInstr::mod_neg);
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shader.emit_instruction(ir);
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return true;
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}
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static bool
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emit_any_all_icomp(const nir_alu_instr& alu, EAluOp op, int nc, bool all, Shader& shader)
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{
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/* This should probabyl be lowered in nir */
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auto& value_factory = shader.value_factory();
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AluInstr *ir = nullptr;
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PRegister v[6];
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auto dest = value_factory.dest(alu.def, 0, pin_free);
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for (int i = 0; i < nc + nc / 2; ++i)
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v[i] = value_factory.temp_register();
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EAluOp combine = all ? op2_and_int : op2_or_int;
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for (int i = 0; i < nc; ++i) {
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ir = new AluInstr(op,
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v[i],
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value_factory.src(alu.src[0], i),
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value_factory.src(alu.src[1], i),
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AluInstr::write);
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shader.emit_instruction(ir);
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}
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if (ir)
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ir->set_alu_flag(alu_last_instr);
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if (nc == 2) {
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ir = new AluInstr(combine, dest, v[0], v[1], AluInstr::last_write);
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shader.emit_instruction(ir);
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return true;
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}
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if (nc == 3) {
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ir = new AluInstr(combine, v[3], v[0], v[1], AluInstr::last_write);
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shader.emit_instruction(ir);
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ir = new AluInstr(combine, dest, v[3], v[2], AluInstr::last_write);
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shader.emit_instruction(ir);
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return true;
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}
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if (nc == 4) {
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ir = new AluInstr(combine, v[4], v[0], v[1], AluInstr::write);
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shader.emit_instruction(ir);
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ir = new AluInstr(combine, v[5], v[2], v[3], AluInstr::last_write);
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shader.emit_instruction(ir);
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ir = new AluInstr(combine, dest, v[4], v[5], AluInstr::last_write);
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shader.emit_instruction(ir);
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return true;
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}
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return false;
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}
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static bool
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emit_dot(const nir_alu_instr& alu, int n, Shader& shader)
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{
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@ -625,14 +625,6 @@ r600_lower_to_scalar_instr_filter(const nir_instr *instr, const void *)
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auto alu = nir_instr_as_alu(instr);
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switch (alu->op) {
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case nir_op_bany_fnequal3:
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case nir_op_bany_fnequal4:
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case nir_op_ball_fequal3:
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case nir_op_ball_fequal4:
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case nir_op_bany_inequal3:
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case nir_op_bany_inequal4:
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case nir_op_ball_iequal3:
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case nir_op_ball_iequal4:
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case nir_op_fdot2:
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case nir_op_fdot3:
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case nir_op_fdot4:
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