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radv: don't shrink image stores for The Surge 2

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The game seems to declare the wrong format.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes: e4d75c22 ("nir/opt_shrink_vectors: shrink image stores using the format")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4347
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9229>
(cherry picked from commit 21697082ec)
This commit is contained in:
Rhys Perry 2021-02-23 19:33:02 +00:00 • committed by Dylan Baker
parent 089c01ffd7
commit 43bb5f818a
8 changed files with 28 additions and 11 deletions
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2
.pick_status.json
View file

@ -922,7 +922,7 @@
"description": "radv: don't shrink image stores for The Surge 2",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"master_sha": null,
"because_sha": "e4d75c22beba5533b499f7f8f8be6ab0a110ecbc"
},

5
src/amd/vulkan/radv_device.c
View file

@ -640,6 +640,10 @@ radv_handle_per_app_options(struct radv_instance *instance,
driQueryOptionb(&instance->dri_options,
"radv_enable_mrt_output_nan_fixup");
instance->disable_shrink_image_store =
driQueryOptionb(&instance->dri_options,
"radv_disable_shrink_image_store");
if (driQueryOptionb(&instance->dri_options, "radv_no_dynamic_bounds"))
instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
}
@ -652,6 +656,7 @@ static const driOptionDescription radv_dri_options[] = {
DRI_CONF_VK_X11_ENSURE_MIN_IMAGE_COUNT(false)
DRI_CONF_RADV_REPORT_LLVM9_VERSION_STRING(false)
DRI_CONF_RADV_ENABLE_MRT_OUTPUT_NAN_FIXUP(false)
DRI_CONF_RADV_DISABLE_SHRINK_IMAGE_STORE(false)
DRI_CONF_RADV_NO_DYNAMIC_BOUNDS(false)
DRI_CONF_RADV_OVERRIDE_UNIFORM_OFFSET_ALIGNMENT(0)
DRI_CONF_SECTION_END

8
src/amd/vulkan/radv_pipeline.c
View file

@ -2361,7 +2361,8 @@ radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders,
if (nir_lower_io_to_scalar_early(ordered_shaders[i], mask)) {
/* Optimize the new vector code and then remove dead vars */
nir_copy_prop(ordered_shaders[i]);
nir_opt_shrink_vectors(ordered_shaders[i], true);
nir_opt_shrink_vectors(ordered_shaders[i],
!pipeline->device->instance->disable_shrink_image_store);
if (ordered_shaders[i]->info.stage != last) {
/* Optimize swizzled movs of load_const for
@ -3303,7 +3304,7 @@ VkResult radv_create_shaders(struct radv_pipeline *pipeline,
for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
if (nir[i]) {
radv_start_feedback(stage_feedbacks[i]);
radv_optimize_nir(nir[i], optimize_conservatively, false);
radv_optimize_nir(device, nir[i], optimize_conservatively, false);
radv_stop_feedback(stage_feedbacks[i], false);
}
}
@ -3349,7 +3350,8 @@ VkResult radv_create_shaders(struct radv_pipeline *pipeline,
radv_lower_io(device, nir[i]);
lower_to_scalar |= nir_opt_shrink_vectors(nir[i], true);
lower_to_scalar |= nir_opt_shrink_vectors(nir[i],
!device->instance->disable_shrink_image_store);
if (lower_to_scalar)
nir_lower_alu_to_scalar(nir[i], NULL, NULL);

1
src/amd/vulkan/radv_private.h
View file

@ -361,6 +361,7 @@ struct radv_instance {
*/
bool enable_mrt_output_nan_fixup;
bool disable_tc_compat_htile_in_general;
bool disable_shrink_image_store;
};
VkResult radv_init_wsi(struct radv_physical_device *physical_device);

11
src/amd/vulkan/radv_shader.c
View file

@ -172,8 +172,8 @@ void radv_DestroyShaderModule(
}
void
radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
bool allow_copies)
radv_optimize_nir(const struct radv_device *device, struct nir_shader *shader,
bool optimize_conservatively, bool allow_copies)
{
bool progress;
unsigned lower_flrp =
@ -243,7 +243,8 @@ radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
}
NIR_PASS(progress, shader, nir_opt_undef);
NIR_PASS(progress, shader, nir_opt_shrink_vectors, true);
NIR_PASS(progress, shader, nir_opt_shrink_vectors,
!device->instance->disable_shrink_image_store);
if (shader->options->max_unroll_iterations) {
NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
}
@ -650,7 +651,7 @@ radv_shader_compile_to_nir(struct radv_device *device,
nir_lower_load_const_to_scalar(nir);
if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
radv_optimize_nir(nir, false, true);
radv_optimize_nir(device, nir, false, true);
/* call radv_nir_lower_ycbcr_textures() late as there might still be
* tex with undef texture/sampler before first optimization */
@ -697,7 +698,7 @@ radv_shader_compile_to_nir(struct radv_device *device,
!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT) &&
nir->info.stage != MESA_SHADER_COMPUTE) {
/* Optimize the lowered code before the linking optimizations. */
radv_optimize_nir(nir, false, false);
radv_optimize_nir(device, nir, false, false);
}
return nir;

4
src/amd/vulkan/radv_shader.h
View file

@ -422,8 +422,8 @@ struct radv_shader_slab {
};
void
radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
bool allow_copies);
radv_optimize_nir(const struct radv_device *device, struct nir_shader *shader,
bool optimize_conservatively, bool allow_copies);
bool
radv_nir_lower_ycbcr_textures(nir_shader *shader,
const struct radv_pipeline_layout *layout);

4
src/util/00-mesa-defaults.conf
View file

@ -732,6 +732,10 @@ TODO: document the other workarounds.
<option name="radv_no_dynamic_bounds" value="true" />
</application>
<application name="The Surge 2" application_name_match="Fledge">
<option name="radv_disable_shrink_image_store" value="true" />
</application>
<application name="World War Z" application_name_match="WWZ">
<option name="radv_override_uniform_offset_alignment" value="16" />
</application>

4
src/util/driconf.h
View file

@ -450,6 +450,10 @@
DRI_CONF_OPT_B(radv_no_dynamic_bounds, def, \
"Disabling bounds checking for dynamic buffer descriptors")
#define DRI_CONF_RADV_DISABLE_SHRINK_IMAGE_STORE(def) \
DRI_CONF_OPT_B(radv_disable_shrink_image_store, def, \
"Disabling shrinking of image stores based on the format")
#define DRI_CONF_RADV_OVERRIDE_UNIFORM_OFFSET_ALIGNMENT(def) \
DRI_CONF_OPT_I(radv_override_uniform_offset_alignment, def, 0, 128, \
"Override the minUniformBufferOffsetAlignment exposed to the application. (0 = default)")