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ir3: Add support for VK_QCOM_image_processing opcodes.

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Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38559>
This commit is contained in:
Emma Anholt 2025-11-21 22:03:53 -08:00 • committed by Marge Bot
parent bd6c1fea1f
commit 431c7a6e36
8 changed files with 125 additions and 4 deletions
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4
src/freedreno/ir3/disasm-a3xx.c
View file

@ -320,6 +320,10 @@ static const struct opc_info {
OPC(5, OPC_QUAD_SHUFFLE_VERT, quad_shuffle.vert),
OPC(5, OPC_QUAD_SHUFFLE_DIAG, quad_shuffle.diag),
OPC(5, OPC_TCINV, tcinv),
OPC(5, OPC_IMG_BINDLESS_HOF, img_bindless_hof),
OPC(5, OPC_IMG_BINDLESS_PCMN, img_bindless_pcmn),
OPC(5, OPC_IMG_BINDLESS, img_bindless),
/* macros are needed here for ir3_print */
OPC(5, OPC_DSXPP_MACRO, dsxpp.macro),
OPC(5, OPC_DSYPP_MACRO, dsypp.macro),

7
src/freedreno/ir3/instr-a3xx.h
View file

@ -259,9 +259,12 @@ typedef enum {
OPC_QUAD_SHUFFLE_VERT = _OPC(5, 31),
OPC_QUAD_SHUFFLE_DIAG = _OPC(5, 32),
OPC_TCINV = _OPC(5, 33),
OPC_IMG_BINDLESS_HOF = _OPC(5, 34),
OPC_IMG_BINDLESS_PCMN = _OPC(5, 35),
OPC_IMG_BINDLESS = _OPC(5, 36),
/* cat5 meta instructions, placed above the cat5 opc field's size */
OPC_DSXPP_MACRO = _OPC(5, 35),
OPC_DSYPP_MACRO = _OPC(5, 36),
OPC_DSXPP_MACRO = _OPC(5, 37),
OPC_DSYPP_MACRO = _OPC(5, 38),
/* category 6: */
OPC_LDG = _OPC(6, 0), /* load-global */

4
src/freedreno/ir3/ir3.h
View file

@ -475,6 +475,10 @@ struct ir3_instruction {
unsigned tex_base : 3;
unsigned cluster_size : 4;
type_t type;
enum {
IR3_MATCH_MODE_SAD = 0, /* Sum of Absolute Difference */
IR3_MATCH_MODE_SSD = 1, /* Sum of Squared Differences */
} match_mode; /* for block matching textures */
} cat5;
struct {
type_t type;

6
src/freedreno/ir3/ir3_lexer.l
View file

@ -360,6 +360,9 @@ static int parse_reg(const char *str)
"quad_shuffle.vert" return TOKEN(T_OP_QSHUFFLE_V);
"quad_shuffle.diag" return TOKEN(T_OP_QSHUFFLE_DIAG);
"tcinv" return TOKEN(T_OP_TCINV);
"img_bindless.hof" return TOKEN(T_OP_IMG_BINDLESS_HOF);
"img_bindless.pcmn" return TOKEN(T_OP_IMG_BINDLESS_PCMN);
"img_bindless" return TOKEN(T_OP_IMG_BINDLESS);
/* category 6: */
"ldg" return TOKEN(T_OP_LDG);
@ -482,6 +485,9 @@ static int parse_reg(const char *str)
"3d" return TOKEN(T_3D);
"4d" return TOKEN(T_4D);
"sad" return TOKEN(T_SAD);
"ssd" return TOKEN(T_SSD);
"lt" return TOKEN(T_LT);
"le" return TOKEN(T_LE);
"gt" return TOKEN(T_GT);

13
src/freedreno/ir3/ir3_parser.y
View file

@ -303,6 +303,9 @@ static void print_token(FILE *file, int type, YYSTYPE value)
%token <tok> T_OP_QSHUFFLE_V
%token <tok> T_OP_QSHUFFLE_DIAG
%token <tok> T_OP_TCINV
%token <tok> T_OP_IMG_BINDLESS_HOF
%token <tok> T_OP_IMG_BINDLESS_PCMN
%token <tok> T_OP_IMG_BINDLESS
/* category 6: */
%token <tok> T_OP_LDG
@ -426,6 +429,9 @@ static void print_token(FILE *file, int type, YYSTYPE value)
%token <tok> T_3D
%token <tok> T_4D
%token <tok> T_SAD
%token <tok> T_SSD
/* condition qualifiers: */
%token <tok> T_LT
%token <tok> T_LE
@ -923,6 +929,12 @@ cat5_opc: T_OP_ISAML { new_instr(OPC_ISAML); }
| T_OP_QSHUFFLE_H { new_instr(OPC_QUAD_SHUFFLE_HORIZ); }
| T_OP_QSHUFFLE_V { new_instr(OPC_QUAD_SHUFFLE_VERT); }
| T_OP_QSHUFFLE_DIAG { new_instr(OPC_QUAD_SHUFFLE_DIAG); }
| T_OP_IMG_BINDLESS_PCMN { new_instr(OPC_IMG_BINDLESS_PCMN); }
| T_OP_IMG_BINDLESS_HOF { new_instr(OPC_IMG_BINDLESS_HOF); }
| T_OP_IMG_BINDLESS { new_instr(OPC_IMG_BINDLESS); }
cat5_matchmode: '.' T_SAD { instr->cat5.match_mode = IR3_MATCH_MODE_SAD; }
| '.' T_SSD { instr->cat5.match_mode = IR3_MATCH_MODE_SSD; }
cat5_flag: '.' T_3D { instr->flags |= IR3_INSTR_3D; }
| '.' 'a' { instr->flags |= IR3_INSTR_A; }
@ -937,6 +949,7 @@ cat5_flag: '.' T_3D { instr->flags |= IR3_INSTR_3D; }
| '.' T_W { instr->cat5.cluster_size = $2; }
| '.' T_RCK { instr->flags |= IR3_INSTR_RCK; }
| '.' T_CLP { instr->flags |= IR3_INSTR_CLP; }
| cat5_matchmode
cat5_flags:
| cat5_flag cat5_flags

6
src/freedreno/ir3/ir3_print.c
View file

@ -257,6 +257,12 @@ print_instr_name(struct log_stream *stream, struct ir3_instruction *instr,
mesa_log_stream_printf(stream, ".%s", type_name(instr->cat6.type));
break;
case OPC_IMG_BINDLESS: {
mesa_log_stream_printf(
stream, ".%s",
instr->cat5.match_mode == IR3_MATCH_MODE_SSD ? "ssd" : "sad");
break;
}
case OPC_ALIAS:
switch (instr->cat7.alias_scope) {
case ALIAS_TEX:

15
src/freedreno/ir3/tests/disasm.c
View file

@ -201,6 +201,21 @@ static const struct test {
INSTR_7XX(a02c3f06_c2041003, "isam.v.base0 (u32)(xyzw)r1.z, r0.y+8, s#0, t#1"),
INSTR_7XX(a02c3f05_a1240601, "isam.v.s2en.uniform.base0 (u32)(xyzw)r1.y, r0.x+3, r2.y"),
INSTR_7XX(a7581f00_e0014001, "img_bindless.sad.base0 (f32)(xyzw)r0.x, r0.x, r40.x, t#0, a1.x"), /* img_bindless.s2en.mode7.sad.base0 (f32)(xyzw)r0.x, r0.x, r40.x, 0 */
INSTR_7XX(a75c1f00_e0014001, "img_bindless.ssd.base0 (f32)(xyzw)r0.x, r0.x, r40.x, t#0, a1.x"), /* img_bindless.s2en.mode7.ssd.base0 (f32)(xyzw)r0.x, r0.x, r40.x, 0 */
INSTR_7XX(a7581f00_a0014541, "img_bindless.sad.s2en.uniform.base0 (f32)(xyzw)r0.x, r40.x, r40.z, r0.x"),
INSTR_7XX(a7581f00_e1414541, "img_bindless.sad.base0 (f32)(xyzw)r0.x, r40.x, r40.z, t#10, a1.x"),
/* dEQP-VK.image_processing.graphics.monolithic.block_matching.sad.basic.r8_unorm_diff (a750) */
INSTR_7XX(a7581104_e0014001, "img_bindless.sad.base0 (f32)(x)r1.x, r0.x, r40.x, t#0, a1.x"), /* img_bindless.o.s2en.mode7.sad.base0 (f32)(xOOO)r1.x, r0.x, r40.x, 0; */
/* dEQP-VK.image_processing.graphics.monolithic.block_matching.ssd.basic.r8_unorm_diff (a750) */
INSTR_7XX(a75c1104_e0014001, "img_bindless.ssd.base0 (f32)(x)r1.x, r0.x, r40.x, t#0, a1.x"), /* img_bindless.o.s.s2en.mode7.ssd.base0 (f32)(xOOO)r1.x, r0.x, r40.x, 0; */
/* dEQP-VK.image_processing.compute.box_filter_sampling.box_filter.* (a750) */
INSTR_7XX(a74c1f00_c0214541, "img_bindless.pcmn.base0 (f32)(xyzw)r0.x, r40.x, r40.z, s#1, t#0"), /* img_bindless.s.s2en.mode6.pcmn.base0 (f32)(xyzw)r0.x, r40.x, r40.z, 1; */
/* dEQP-VK.image_processing.graphics.monolithic.weight_image_sampling.weight_sampling.basic.r8_unorm_weight_r8_unorm_random_subtexel (a750) */
INSTR_7XX(a7481f00_e0000141, "img_bindless.hof.base0 (f32)(xyzw)r0.x, r40.x, t#0, a1.x"), /* img_bindless.s2en.mode7.hof.base0 (f32)(xyzw)r0.x, r40.x, 0; */
/* dEQP-VK.subgroups.arithmetic.compute.subgroupadd_float */
INSTR_6XX(a7c03102_00100003, "brcst.active.w8 (u32)(x)r0.z, r0.y"), /* brcst.active.w8 (u32)(xOOO)r0.z, r0.y */
/* dEQP-VK.subgroups.quad.graphics.subgroupquadbroadcast_int */

74
src/freedreno/isa/ir3-cat5.xml
View file

@ -97,7 +97,6 @@ SOFTWARE.
<field name="3D" pos="48" type="bool" display=".3d"/>
<field name="A" pos="49" type="bool" display=".a"/>
<field name="S2EN_BINDLESS" pos="51" type="bool"/>
<field name="O" pos="52" type="bool" display=".o"/>
<!-- OPC -->
<field name="JP" pos="59" type="bool" display="(jp)"/>
<field name="SY" pos="60" type="bool" display="(sy)"/>
@ -137,7 +136,7 @@ SOFTWARE.
The s2en (indirect) or bindless case
</doc>
<display>
{SY}{JP}{NAME}{3D}{A}{O}{P}{SV}{S2EN}{UNIFORM}{NONUNIFORM}{BASE}{1D}{CLP}{RCK} {TYPE}({WRMASK}){DST_HALF}{DST}{SRC1}{SRC2}{SRC3}{A1}
{SY}{JP}{NAME}{3D}{A}{O}{P}{SV}{MATCH_MODE}{S2EN}{UNIFORM}{NONUNIFORM}{BASE}{1D}{CLP}{RCK} {TYPE}({WRMASK}){DST_HALF}{DST}{SRC1}{SRC2}{SRC3}{A1}
</display>
<field name="BASE_HI" low="19" high="20" type="uint"/>
<field name="SRC3" low="21" high="28" type="#cat5-src3">
@ -156,6 +155,7 @@ SOFTWARE.
<derived name="UNIFORM" expr="#cat5-s2enb-is-uniform" type="bool" display=".uniform"/>
<derived name="NONUNIFORM" expr="#cat5-s2enb-is-nonuniform" type="bool" display=".nonuniform"/>
<derived name="A1" expr="#cat5-s2enb-uses_a1" type="bool" display=", a1.x"/>
<derived name="MATCH_MODE" expr="#false" type="bool" display=""/>
</override>
<assert low="19" high="20">00</assert> <!-- BASE_HI -->
@ -165,6 +165,7 @@ SOFTWARE.
<field name="CLP" pos="18" type="bool" display=".clp"/>
<field name="SV" pos="50" type="bool" display=".s"/>
<field name="P" pos="53" type="bool" display=".p"/>
<field name="O" pos="52" type="bool" display=".o"/>
<derived name="1D" expr="#false" type="bool" display=""/>
<encode>
@ -186,6 +187,7 @@ SOFTWARE.
without it set. The blob disassembles it as .1d when not set. -->
<field name="1D" pos="18" type="bool_inv" display=".1d"/>
<field name="SV" pos="50" type="bool" display=".v"/>
<field name="O" pos="52" type="bool" display=".o"/>
<field name="SRC2_IMM_OFFSET" pos="53" type="bool"/>
<encode>
@ -195,6 +197,73 @@ SOFTWARE.
</encode>
</bitset>
<enum name="#cat5-block-match-mode">
<value val="0" display=".sad">
<doc>
Sum of Absolute Difference
</doc>
</value>
<value val="1" display=".ssd">
<doc>
Sum of Squared Difference
</doc>
</value>
</enum>
<bitset name="img_bindless.hof" extends="#instruction-cat5-tex-base">
<doc>
Higher order filtering -- SampleWeighted from VK_QCOM_image_processing.
</doc>
<derived name="NUM_SRC" expr="#one" type="uint"/>
<derived name="HAS_SAMP" expr="#true" type="bool"/>
<derived name="HAS_TEX" expr="#true" type="bool"/>
<derived name="HAS_TYPE" expr="#true" type="bool"/>
<derived name="SV" expr="#false" type="bool" display=""/>
<derived name="CLP" expr="#false" type="bool" display=""/>
<derived name="O" expr="#false" type="bool" display=""/>
<pattern low="52" high="58">1110100</pattern>
<pattern low="50" high="50">0</pattern>
<pattern pos="18">0</pattern>
</bitset>
<bitset name="img_bindless.pcmn" extends="#instruction-cat5-tex-base">
<doc>
Phase-controlled M/N downscale filtering -- BoxFilter from VK_QCOM_image_processing.
</doc>
<derived name="NUM_SRC" expr="#two" type="uint"/>
<derived name="HAS_SAMP" expr="#true" type="bool"/>
<derived name="HAS_TEX" expr="#true" type="bool"/>
<derived name="HAS_TYPE" expr="#true" type="bool"/>
<derived name="SV" expr="#false" type="bool" display=""/>
<derived name="CLP" expr="#false" type="bool" display=""/>
<derived name="O" expr="#false" type="bool" display=""/>
<pattern low="52" high="58">1110100</pattern>
<pattern low="50" high="50">1</pattern>
<pattern pos="18">0</pattern>
</bitset>
<bitset name="img_bindless" extends="#instruction-cat5-tex-base">
<doc>
SAD/SSD block matching from VK_QCOM_image_processing.
</doc>
<derived name="NUM_SRC" expr="#two" type="uint"/>
<derived name="HAS_SAMP" expr="#false" type="bool"/>
<derived name="HAS_TEX" expr="#true" type="bool"/>
<derived name="HAS_TYPE" expr="#true" type="bool"/>
<derived name="SV" expr="#false" type="bool" display=""/>
<derived name="CLP" expr="#false" type="bool" display=""/>
<derived name="O" expr="#false" type="bool" display=""/>
<pattern low="52" high="58">1110101</pattern>
<pattern pos="18">0</pattern>
<field name="MATCH_MODE" pos="50" type="#cat5-block-match-mode"/>
<encode type="struct ir3_instruction *">
<map name="MATCH_MODE">src->cat5.match_mode</map>
</encode>
</bitset>
<bitset name="isaml" extends="#instruction-cat5-tex">
<pattern low="54" high="58">00001</pattern>
<derived name="NUM_SRC" expr="#two" type="uint"/>
@ -518,6 +587,7 @@ SOFTWARE.
<bitset name="#instruction-cat5-brcst" extends="#instruction-cat5">
<pattern pos="18">0</pattern>
<pattern pos="50">0</pattern>
<field name="O" pos="52" type="bool" display=".o"/>
<derived name="CLP" expr="#false" type="bool" display=""/>
</bitset>