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tu/a8xx: add missing register state in tu_clear_sysmem_attachments()
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For depth clears of sysmem attachments to work properly, additional
register state is required in tu_clear_sysmem_attachments().

Fixes various CTS tests on a8xx:
  - dEQP-VK.conditional_rendering.draw_clear.clear.depth.*
  - dEQP-VK.api.image_clearing.core.clear_depth_stencil_attachment.*
    with FD_DEV_FEATURES=has_generic_clear=0, which will result in
    tu_clear_sysmem_attachments() fallback being used

Signed-off-by: Zan Dobersek <zdobersek@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40542>
This commit is contained in:
Zan Dobersek 2026-03-20 17:38:50 +01:00 • committed by Marge Bot
parent a6992c7bbe
commit 42ea820b26
1 changed files with 14 additions and 1 deletions
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15
src/freedreno/vulkan/tu_clear_blit.cc
View file

@ -4368,9 +4368,22 @@ tu_clear_sysmem_attachments(struct tu_cmd_buffer *cmd,
tu_cs_emit_regs(cs, A6XX_RB_DEPTH_CNTL(
.z_test_enable = z_clear,
.z_write_enable = z_clear,
.zfunc = FUNC_ALWAYS));
.zfunc = FUNC_ALWAYS,
.z_clamp_enable = CHIP >= A7XX,
.o_depth_01_clamp_en = CHIP >= A8XX));
tu_cs_emit_regs(cs, A6XX_RB_DEPTH_BOUND_MIN(0.0),
A6XX_RB_DEPTH_BOUND_MAX(1.0));
tu_cs_emit_regs(cs, GRAS_SU_DEPTH_CNTL(CHIP, z_clear));
tu_cs_emit_regs(cs, GRAS_SU_DEPTH_PLANE_CNTL(CHIP));
tu_cs_emit_regs(cs, GRAS_CL_VIEWPORT_ZCLAMP_MIN(CHIP, 0, 0.0));
tu_cs_emit_regs(cs, GRAS_CL_VIEWPORT_ZCLAMP_MAX(CHIP, 0, 1.0));
if (CHIP >= A8XX) {
tu_cs_emit_regs(cs, RB_VIEWPORT_ZCLAMP_MIN_REG(CHIP, 0, 0.0));
tu_cs_emit_regs(cs, RB_VIEWPORT_ZCLAMP_MAX_REG(CHIP, 0, 1.0));
} else {
tu_cs_emit_regs(cs, RB_VIEWPORT_ZCLAMP_MIN(CHIP, 0.0));
tu_cs_emit_regs(cs, RB_VIEWPORT_ZCLAMP_MAX(CHIP, 1.0));
}
tu_cs_emit_regs(cs, A6XX_RB_STENCIL_CNTL(
.stencil_enable = s_clear,
.func = FUNC_ALWAYS,