diff --git a/src/amd/vulkan/meta/radv_meta.h b/src/amd/vulkan/meta/radv_meta.h
index a1dae141bb4..dcd76b83275 100644
--- a/src/amd/vulkan/meta/radv_meta.h
+++ b/src/amd/vulkan/meta/radv_meta.h
@@ -214,12 +214,14 @@ void radv_meta_clear_image_cs(struct radv_cmd_buffer *cmd_buffer, struct radv_me
 void radv_expand_depth_stencil(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
                                const VkImageSubresourceRange *subresourceRange,
                                struct radv_sample_locations_state *sample_locs);
-void radv_fast_clear_flush_image_inplace(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
-                                         const VkImageSubresourceRange *subresourceRange);
 void radv_decompress_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
                          const VkImageSubresourceRange *subresourceRange);
 void radv_retile_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image);
 
+void radv_fast_clear_eliminate(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
+                               const VkImageSubresourceRange *subresourceRange);
+void radv_fmask_decompress(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
+                           const VkImageSubresourceRange *subresourceRange);
 void radv_fmask_color_expand(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
                              const VkImageSubresourceRange *subresourceRange);
 
diff --git a/src/amd/vulkan/meta/radv_meta_fast_clear.c b/src/amd/vulkan/meta/radv_meta_fast_clear.c
index 47046970568..f3823784fa2 100644
--- a/src/amd/vulkan/meta/radv_meta_fast_clear.c
+++ b/src/amd/vulkan/meta/radv_meta_fast_clear.c
@@ -413,7 +413,7 @@ radv_process_color_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *
       radv_update_dcc_metadata(cmd_buffer, image, subresourceRange, false);
 }
 
-static void
+void
 radv_fast_clear_eliminate(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
                           const VkImageSubresourceRange *subresourceRange)
 {
@@ -425,7 +425,7 @@ radv_fast_clear_eliminate(struct radv_cmd_buffer *cmd_buffer, struct radv_image
    radv_process_color_image(cmd_buffer, image, subresourceRange, FAST_CLEAR_ELIMINATE);
 }
 
-static void
+void
 radv_fmask_decompress(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
                       const VkImageSubresourceRange *subresourceRange)
 {
@@ -437,33 +437,6 @@ radv_fmask_decompress(struct radv_cmd_buffer *cmd_buffer, struct radv_image *ima
    radv_process_color_image(cmd_buffer, image, subresourceRange, FMASK_DECOMPRESS);
 }
 
-void
-radv_fast_clear_flush_image_inplace(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
-                                    const VkImageSubresourceRange *subresourceRange)
-{
-   /* FMASK_DECOMPRESS is only required for MSAA images that don't support TC-compat CMASK. */
-   const bool needs_fmask_decompress = radv_image_has_fmask(image) && !image->tc_compatible_cmask;
-
-   /* FCE is only required for color images that don't support comp-to-single fast clears. */
-   const bool needs_fce = !image->support_comp_to_single;
-
-   if (needs_fmask_decompress) {
-      /* MSAA images with DCC and CMASK might have been fast-cleared and might require a FCE but
-       * FMASK_DECOMPRESS can't eliminate DCC fast clears. Only GFX10 is affected because it has few
-       * restrictions related to comp-to-single.
-       */
-      const bool needs_dcc_fce =
-         radv_image_has_dcc(image) && radv_image_has_cmask(image) && !image->support_comp_to_single;
-
-      if (needs_dcc_fce)
-         radv_fast_clear_eliminate(cmd_buffer, image, subresourceRange);
-
-      radv_fmask_decompress(cmd_buffer, image, subresourceRange);
-   } else if (needs_fce) {
-      radv_fast_clear_eliminate(cmd_buffer, image, subresourceRange);
-   }
-}
-
 static void
 radv_decompress_dcc_compute(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
                             const VkImageSubresourceRange *subresourceRange)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 5421ae82b18..a05b04fddb5 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -12699,7 +12699,27 @@ radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer, struct ra
    if (needs_dcc_decompress) {
       radv_decompress_dcc(cmd_buffer, image, range);
    } else if (needs_fast_clear_flush) {
-      radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
+      /* FMASK_DECOMPRESS is only required for MSAA images that don't support TC-compat CMASK. */
+      const bool needs_fmask_decompress = radv_image_has_fmask(image) && !image->tc_compatible_cmask;
+
+      /* FCE is only required for color images that don't support comp-to-single fast clears. */
+      const bool needs_fce = !image->support_comp_to_single;
+
+      if (needs_fmask_decompress) {
+         /* MSAA images with DCC and CMASK might have been fast-cleared and might require a FCE but
+          * FMASK_DECOMPRESS can't eliminate DCC fast clears. Only GFX10 is affected because it has few
+          * restrictions related to comp-to-single.
+          */
+         const bool needs_dcc_fce =
+            radv_image_has_dcc(image) && radv_image_has_cmask(image) && !image->support_comp_to_single;
+
+         if (needs_dcc_fce)
+            radv_fast_clear_eliminate(cmd_buffer, image, range);
+
+         radv_fmask_decompress(cmd_buffer, image, range);
+      } else if (needs_fce) {
+         radv_fast_clear_eliminate(cmd_buffer, image, range);
+      }
    }
 
    if (needs_fmask_color_expand)