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pan/bi: Don't allow spilling coverage mask writes

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The register precolouring logic assumes that coverage masks are always in R60,
so spilling them causes incorrect results. We could do better. Fixes on Valhall:

   dEQP-GLES3.functional.ubo.random.all_per_block_buffers.28

Fixes: 3df5446cbd ("pan/bi: Simplify register precolouring in the IR")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16748>
This commit is contained in:
Alyssa Rosenzweig 2022-05-27 11:36:01 -04:00 • committed by Marge Bot
parent 67f5721349
commit 42a4a123a6
1 changed files with 14 additions and 1 deletions
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15
src/panfrost/bifrost/bi_ra.c
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@ -497,8 +497,21 @@ bi_choose_spill_node(bi_context *ctx, struct lcra_state *l)
bi_foreach_dest(ins, d) {
unsigned node = bi_get_node(ins->dest[d]);
if (node < l->node_count && ins->no_spill)
if (node >= l->node_count)
continue;
/* Don't allow spilling coverage mask writes because the
* register preload logic assumes it will stay in R60.
* This could be optimized.
*/
if (ins->no_spill ||
ins->op == BI_OPCODE_ATEST ||
ins->op == BI_OPCODE_ZS_EMIT ||
(ins->op == BI_OPCODE_MOV_I32 &&
ins->src[0].type == BI_INDEX_REGISTER &&
ins->src[0].value == 60)) {
BITSET_SET(no_spill, node);
}
}
}