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i965: Fix texturing in the vec4 TCS and GS backends.

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We were failing to zero m0.2 of the sampler message header for TCS and
GS messages in the simple case.  fs_generator has done this for about
a year now, but we missed it in vec4_generator.

Fixes ES31-CTS.core.texture_cube_map_array.sampling,
GL45-CTS.texture_cube_map_array.sampling, and many
dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler subtests:
- dynamically_uniform.tessellation_control.isampler3d
- dynamically_uniform.tessellation_control.isamplercube
- dynamically_uniform.tessellation_control.sampler2d
- dynamically_uniform.tessellation_control.usamplercube
- dynamically_uniform.tessellation_control.sampler2darray
- dynamically_uniform.tessellation_control.isampler2darray
- dynamically_uniform.tessellation_control.usampler3d
- dynamically_uniform.tessellation_control.usampler2darray
- dynamically_uniform.tessellation_control.usampler2d
- dynamically_uniform.tessellation_control.sampler3d
- dynamically_uniform.tessellation_control.samplercube
- dynamically_uniform.tessellation_control.isampler2d
- uniform.tessellation_control.isampler3d
- uniform.tessellation_control.isamplercube
- uniform.tessellation_control.usampler2d
- uniform.tessellation_control.usampler3d
- uniform.tessellation_control.sampler2darray
- uniform.tessellation_control.isampler2darray
- uniform.tessellation_control.usampler2darray
- uniform.tessellation_control.sampler2d
- uniform.tessellation_control.usamplercube
- uniform.tessellation_control.sampler3d
- uniform.tessellation_control.samplercube
- uniform.tessellation_control.isampler2d

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
This commit is contained in:
Kenneth Graunke 2017-01-06 01:13:24 -08:00
parent c93efb0a4f
commit 4295af646f
1 changed files with 12 additions and 2 deletions
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14
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
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@ -106,6 +106,7 @@ generate_math2_gen4(struct brw_codegen *p,
static void
generate_tex(struct brw_codegen *p,
struct brw_vue_prog_data *prog_data,
gl_shader_stage stage,
vec4_instruction *inst,
struct brw_reg dst,
struct brw_reg src,
@ -238,8 +239,16 @@ generate_tex(struct brw_codegen *p,
*/
dw2 |= GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2;
if (dw2)
/* The VS, DS, and FS stages have the g0.2 payload delivered as 0,
* so header0.2 is 0 when g0 is copied. The HS and GS stages do
* not, so we must set to to 0 to avoid setting undesirable bits
* in the message header.
*/
if (dw2 ||
stage == MESA_SHADER_TESS_CTRL ||
stage == MESA_SHADER_GEOMETRY) {
brw_MOV(p, get_element_ud(header, 2), brw_imm_ud(dw2));
}
brw_adjust_sampler_state_pointer(p, header, sampler_index);
brw_pop_insn_state(p);
@ -1748,7 +1757,8 @@ generate_code(struct brw_codegen *p,
case SHADER_OPCODE_TG4:
case SHADER_OPCODE_TG4_OFFSET:
case SHADER_OPCODE_SAMPLEINFO:
generate_tex(p, prog_data, inst, dst, src[0], src[1], src[2]);
generate_tex(p, prog_data, nir->stage,
inst, dst, src[0], src[1], src[2]);
break;
case VS_OPCODE_URB_WRITE: