From 42877c8b631002f14664733f736bbfb062ba743a Mon Sep 17 00:00:00 2001 From: Jesse Natalie Date: Mon, 22 May 2023 09:59:56 -0700 Subject: [PATCH] dxil: Don't generate load_ubo_dxil directly Just use load_ubo and let it get lowered appropriately later on. Part-of: --- src/gallium/drivers/d3d12/d3d12_compiler.cpp | 1 - src/gallium/drivers/d3d12/d3d12_nir_passes.c | 36 -------------- src/gallium/drivers/d3d12/d3d12_nir_passes.h | 3 -- src/microsoft/clc/clc_nir.c | 52 +++++++++----------- src/microsoft/spirv_to_dxil/dxil_spirv_nir.c | 49 +++++++++++------- src/microsoft/vulkan/dzn_nir.c | 8 +-- 6 files changed, 58 insertions(+), 91 deletions(-) diff --git a/src/gallium/drivers/d3d12/d3d12_compiler.cpp b/src/gallium/drivers/d3d12/d3d12_compiler.cpp index 34d650e2936..73b9a79e065 100644 --- a/src/gallium/drivers/d3d12/d3d12_compiler.cpp +++ b/src/gallium/drivers/d3d12/d3d12_compiler.cpp @@ -138,7 +138,6 @@ compile_nir(struct d3d12_context *ctx, struct d3d12_shader_selector *sel, NIR_PASS_V(nir, nir_lower_clip_halfz); NIR_PASS_V(nir, d3d12_lower_yflip); } - NIR_PASS_V(nir, nir_lower_packed_ubo_loads); NIR_PASS_V(nir, d3d12_lower_load_draw_params); NIR_PASS_V(nir, d3d12_lower_load_patch_vertices_in); NIR_PASS_V(nir, d3d12_lower_state_vars, shader); diff --git a/src/gallium/drivers/d3d12/d3d12_nir_passes.c b/src/gallium/drivers/d3d12/d3d12_nir_passes.c index 2f844401d6a..f04c5ce1604 100644 --- a/src/gallium/drivers/d3d12/d3d12_nir_passes.c +++ b/src/gallium/drivers/d3d12/d3d12_nir_passes.c @@ -628,42 +628,6 @@ d3d12_add_missing_dual_src_target(struct nir_shader *s, nir_metadata_dominance); } -static bool -lower_load_ubo_packed_filter(const nir_instr *instr, - UNUSED const void *_options) { - if (instr->type != nir_instr_type_intrinsic) - return false; - - nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr); - - return intr->intrinsic == nir_intrinsic_load_ubo; -} - -static nir_ssa_def * -lower_load_ubo_packed_impl(nir_builder *b, nir_instr *instr, - UNUSED void *_options) { - nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr); - - nir_ssa_def *buffer = intr->src[0].ssa; - nir_ssa_def *offset = intr->src[1].ssa; - - nir_ssa_def *result = - build_load_ubo_dxil(b, buffer, - offset, - nir_dest_num_components(intr->dest), - nir_dest_bit_size(intr->dest), - nir_intrinsic_align(intr)); - return result; -} - -bool -nir_lower_packed_ubo_loads(nir_shader *nir) { - return nir_shader_lower_instructions(nir, - lower_load_ubo_packed_filter, - lower_load_ubo_packed_impl, - NULL); -} - void d3d12_lower_primitive_id(nir_shader *shader) { diff --git a/src/gallium/drivers/d3d12/d3d12_nir_passes.h b/src/gallium/drivers/d3d12/d3d12_nir_passes.h index 8a39717ab7e..f80d2e6602f 100644 --- a/src/gallium/drivers/d3d12/d3d12_nir_passes.h +++ b/src/gallium/drivers/d3d12/d3d12_nir_passes.h @@ -88,9 +88,6 @@ d3d12_fix_io_uint_type(struct nir_shader *s, uint64_t in_mask, uint64_t out_mask void d3d12_nir_invert_depth(nir_shader *s, unsigned viewport_mask, bool clip_halfz); -bool -nir_lower_packed_ubo_loads(struct nir_shader *nir); - void d3d12_lower_primitive_id(nir_shader *shader); diff --git a/src/microsoft/clc/clc_nir.c b/src/microsoft/clc/clc_nir.c index e5cbbd6e4f8..a5beedf035d 100644 --- a/src/microsoft/clc/clc_nir.c +++ b/src/microsoft/clc/clc_nir.c @@ -31,20 +31,28 @@ #include "clc_compiler.h" #include "../compiler/dxil_nir.h" +static nir_ssa_def * +load_ubo(nir_builder *b, nir_intrinsic_instr *intr, nir_variable *var, unsigned offset) +{ + return nir_build_load_ubo(b, + nir_dest_num_components(intr->dest), + nir_dest_bit_size(intr->dest), + nir_imm_int(b, var->data.binding), + nir_imm_int(b, offset), + .align_mul = 256, + .align_offset = offset, + .range_base = offset, + .range = nir_dest_bit_size(intr->dest) * nir_dest_num_components(intr->dest) / 8); +} + static bool lower_load_base_global_invocation_id(nir_builder *b, nir_intrinsic_instr *intr, nir_variable *var) { b->cursor = nir_after_instr(&intr->instr); - nir_ssa_def *offset = - build_load_ubo_dxil(b, nir_imm_int(b, var->data.binding), - nir_imm_int(b, - offsetof(struct clc_work_properties_data, - global_offset_x)), - nir_dest_num_components(intr->dest), - nir_dest_bit_size(intr->dest), - sizeof(uint32_t) * 4); + nir_ssa_def *offset = load_ubo(b, intr, var, offsetof(struct clc_work_properties_data, + global_offset_x)); nir_ssa_def_rewrite_uses(&intr->dest.ssa, offset); nir_instr_remove(&intr->instr); return true; @@ -56,14 +64,8 @@ lower_load_work_dim(nir_builder *b, nir_intrinsic_instr *intr, { b->cursor = nir_after_instr(&intr->instr); - nir_ssa_def *dim = - build_load_ubo_dxil(b, nir_imm_int(b, var->data.binding), - nir_imm_int(b, - offsetof(struct clc_work_properties_data, - work_dim)), - nir_dest_num_components(intr->dest), - nir_dest_bit_size(intr->dest), - sizeof(uint32_t)); + nir_ssa_def *dim = load_ubo(b, intr, var, offsetof(struct clc_work_properties_data, + work_dim)); nir_ssa_def_rewrite_uses(&intr->dest.ssa, dim); nir_instr_remove(&intr->instr); return true; @@ -76,13 +78,8 @@ lower_load_num_workgroups(nir_builder *b, nir_intrinsic_instr *intr, b->cursor = nir_after_instr(&intr->instr); nir_ssa_def *count = - build_load_ubo_dxil(b, nir_imm_int(b, var->data.binding), - nir_imm_int(b, - offsetof(struct clc_work_properties_data, - group_count_total_x)), - nir_dest_num_components(intr->dest), - nir_dest_bit_size(intr->dest), - sizeof(uint32_t) * 4); + load_ubo(b, intr, var, offsetof(struct clc_work_properties_data, + group_count_total_x)); nir_ssa_def_rewrite_uses(&intr->dest.ssa, count); nir_instr_remove(&intr->instr); return true; @@ -95,13 +92,8 @@ lower_load_base_workgroup_id(nir_builder *b, nir_intrinsic_instr *intr, b->cursor = nir_after_instr(&intr->instr); nir_ssa_def *offset = - build_load_ubo_dxil(b, nir_imm_int(b, var->data.binding), - nir_imm_int(b, - offsetof(struct clc_work_properties_data, - group_id_offset_x)), - nir_dest_num_components(intr->dest), - nir_dest_bit_size(intr->dest), - sizeof(uint32_t) * 4); + load_ubo(b, intr, var, offsetof(struct clc_work_properties_data, + group_id_offset_x)); nir_ssa_def_rewrite_uses(&intr->dest.ssa, offset); nir_instr_remove(&intr->instr); return true; diff --git a/src/microsoft/spirv_to_dxil/dxil_spirv_nir.c b/src/microsoft/spirv_to_dxil/dxil_spirv_nir.c index e591bec7fb8..469ed612d72 100644 --- a/src/microsoft/spirv_to_dxil/dxil_spirv_nir.c +++ b/src/microsoft/spirv_to_dxil/dxil_spirv_nir.c @@ -252,15 +252,16 @@ lower_shader_system_values(struct nir_builder *builder, nir_instr *instr, nir_address_format_bit_size(ubo_format), index, .desc_type = VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER); - unsigned num_components = nir_dest_num_components(intrin->dest); - unsigned alignment = (num_components == 3 ? 4 : num_components) * - nir_dest_bit_size(intrin->dest) / 8; - assert(offset % alignment == 0); - nir_ssa_def *load_data = build_load_ubo_dxil( - builder, nir_channel(builder, load_desc, 0), + nir_ssa_def *load_data = nir_build_load_ubo( + builder, + nir_dest_num_components(intrin->dest), + nir_dest_bit_size(intrin->dest), + nir_channel(builder, load_desc, 0), nir_imm_int(builder, offset), - num_components, nir_dest_bit_size(intrin->dest), - alignment); + .align_mul = 256, + .align_offset = offset, + .range_base = offset, + .range = nir_dest_bit_size(intrin->dest) * nir_dest_num_components(intrin->dest) / 8); nir_ssa_def_rewrite_uses(&intrin->dest.ssa, load_data); nir_instr_remove(instr); @@ -340,11 +341,16 @@ lower_load_push_constant(struct nir_builder *builder, nir_instr *instr, index, .desc_type = VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER); nir_ssa_def *offset = nir_ssa_for_src(builder, intrin->src[0], 1); - nir_ssa_def *load_data = build_load_ubo_dxil( - builder, nir_channel(builder, load_desc, 0), + nir_ssa_def *load_data = nir_build_load_ubo( + builder, + nir_dest_num_components(intrin->dest), + nir_dest_bit_size(intrin->dest), + nir_channel(builder, load_desc, 0), nir_iadd_imm(builder, offset, base), - nir_dest_num_components(intrin->dest), nir_dest_bit_size(intrin->dest), - nir_intrinsic_align(intrin)); + .align_mul = nir_intrinsic_align_mul(intrin), + .align_offset = nir_intrinsic_align_offset(intrin), + .range_base = base, + .range = range); nir_ssa_def_rewrite_uses(&intrin->dest.ssa, load_data); nir_instr_remove(instr); @@ -431,9 +437,13 @@ lower_yz_flip(struct nir_builder *builder, nir_instr *instr, index, .desc_type = VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER); dyn_yz_flip_mask = - build_load_ubo_dxil(builder, - nir_channel(builder, load_desc, 0), - nir_imm_int(builder, offset), 1, 32, 4); + nir_build_load_ubo(builder, 1, 32, + nir_channel(builder, load_desc, 0), + nir_imm_int(builder, offset), + .align_mul = 256, + .align_offset = offset, + .range_base = offset, + .range = 4); *data->reads_sysval_ubo = true; } @@ -728,9 +738,12 @@ write_pntc_with_pos(nir_builder *b, nir_instr *instr, void *_data) index, .desc_type = VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER); nir_ssa_def *transform = nir_channels(b, - build_load_ubo_dxil(b, - nir_channel(b, load_desc, 0), - nir_imm_int(b, offset), 4, 32, 16), + nir_build_load_ubo(b, 4, 32, + nir_channel(b, load_desc, 0), + nir_imm_int(b, offset), + .align_mul = 16, + .range_base = offset, + .range = 16), 0x6); nir_ssa_def *point_center_in_clip = nir_fmul(b, nir_trim_vector(b, pos, 2), nir_frcp(b, nir_channel(b, pos, 3))); diff --git a/src/microsoft/vulkan/dzn_nir.c b/src/microsoft/vulkan/dzn_nir.c index 20f50bd7818..9fef765183f 100644 --- a/src/microsoft/vulkan/dzn_nir.c +++ b/src/microsoft/vulkan/dzn_nir.c @@ -829,10 +829,12 @@ load_dynamic_depth_bias(nir_builder *b, struct dzn_nir_point_gs_info *info) nir_address_format_bit_size(ubo_format), index, .desc_type = VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER); - return build_load_ubo_dxil( - b, nir_channel(b, load_desc, 0), + return nir_build_load_ubo( + b, 1, 32, + nir_channel(b, load_desc, 0), nir_imm_int(b, offset), - 1, 32, 4); + .align_mul = 256, + .align_offset = offset); } nir_shader *