diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index 0aa320d402d..a3803127646 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -1123,6 +1123,21 @@ iris_init_common_context(struct iris_batch *batch)
 #else
 #define IRIS_BT_OFFSET_SHIFT 0
 #endif
+
+#if GFX_VERx10 == 125
+   /* Even though L3 partial write merging is supposed to be enabled
+    * by default on Gfx12.5 according to the hardware spec, i915
+    * appears to accidentally clear the enables during context
+    * initialization, so make sure to enable them here since partial
+    * write merging has a large impact on rendering performance.
+    */
+   iris_emit_reg(batch, GENX(L3SQCREG5), reg) {
+      reg.L3CachePartialWriteMergeTimerInitialValue = 0x7f;
+      reg.CompressiblePartialWriteMergeEnable = true;
+      reg.CoherentPartialWriteMergeEnable = true;
+      reg.CrossTilePartialWriteMergeEnable = true;
+   }
+#endif
 }
 
 static void
diff --git a/src/intel/genxml/gen125.xml b/src/intel/genxml/gen125.xml
index 3ba0685c0be..fd330fe4371 100644
--- a/src/intel/genxml/gen125.xml
+++ b/src/intel/genxml/gen125.xml
@@ -7524,6 +7524,12 @@
     <field name="DC Allocation" start="18" end="24" type="uint" />
     <field name="All Allocation" start="25" end="31" type="uint" />
   </register>
+  <register name="L3SQCREG5" length="1" num="0xB158">
+    <field name="L3 Cache Partial Write Merge Timer Initial Value" start="0" end="9" type="uint" />
+    <field name="Compressible Partial Write Merge Enable" start="21" end="21" type="uint" />
+    <field name="Coherent Partial Write Merge Enable" start="22" end="22" type="uint" />
+    <field name="Cross-Tile Partial Write Merge Enable" start="23" end="23" type="uint" />
+  </register>
   <register name="PS_INVOCATION_COUNT" length="2" num="0x2348">
     <field name="PS Invocation Count Report" start="0" end="63" type="uint" />
   </register>
diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
index b543d94142f..16f95b758a5 100644
--- a/src/intel/vulkan/genX_state.c
+++ b/src/intel/vulkan/genX_state.c
@@ -179,6 +179,21 @@ init_common_queue_state(struct anv_queue *queue, struct anv_batch *batch)
    device->l3_config = cfg;
 #endif
 
+#if GFX_VERx10 == 125
+   /* Even though L3 partial write merging is supposed to be enabled
+    * by default on Gfx12.5 according to the hardware spec, i915
+    * appears to accidentally clear the enables during context
+    * initialization, so make sure to enable them here since partial
+    * write merging has a large impact on rendering performance.
+    */
+   anv_batch_write_reg(batch, GENX(L3SQCREG5), reg) {
+      reg.L3CachePartialWriteMergeTimerInitialValue = 0x7f;
+      reg.CompressiblePartialWriteMergeEnable = true;
+      reg.CoherentPartialWriteMergeEnable = true;
+      reg.CrossTilePartialWriteMergeEnable = true;
+   }
+#endif
+
 #if GFX_VER >= 125
    /* Wa_14014427904 - We need additional invalidate/flush when
     * emitting NP state commands with ATS-M in compute mode.