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hasvk: Rip out scratch surfaces

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These are a DG2+ thing

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19852>
This commit is contained in:
Jason Ekstrand 2022-09-03 00:00:51 -05:00 • committed by Marge Bot
parent eea49c7d32
commit 4256d2cbc2
3 changed files with 0 additions and 83 deletions
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59
src/intel/vulkan_hasvk/anv_allocator.c
View file

@ -1431,13 +1431,6 @@ anv_scratch_pool_finish(struct anv_device *device, struct anv_scratch_pool *pool
anv_device_release_bo(device, pool->bos[i][s]);
}
}
for (unsigned i = 0; i < 16; i++) {
if (pool->surf_states[i].map != NULL) {
anv_state_pool_free(&device->surface_state_pool,
pool->surf_states[i]);
}
}
}
struct anv_bo *
@ -1454,14 +1447,6 @@ anv_scratch_pool_alloc(struct anv_device *device, struct anv_scratch_pool *pool,
const struct intel_device_info *devinfo = device->info;
/* On GFX version 12.5, scratch access changed to a surface-based model.
* Instead of each shader type having its own layout based on IDs passed
* from the relevant fixed-function unit, all scratch access is based on
* thread IDs like it always has been for compute.
*/
if (devinfo->verx10 >= 125)
stage = MESA_SHADER_COMPUTE;
struct anv_bo *bo = p_atomic_read(&pool->bos[scratch_size_log2][stage]);
if (bo != NULL)
@ -1506,50 +1491,6 @@ anv_scratch_pool_alloc(struct anv_device *device, struct anv_scratch_pool *pool,
}
}
uint32_t
anv_scratch_pool_get_surf(struct anv_device *device,
struct anv_scratch_pool *pool,
unsigned per_thread_scratch)
{
if (per_thread_scratch == 0)
return 0;
unsigned scratch_size_log2 = ffs(per_thread_scratch / 2048);
assert(scratch_size_log2 < 16);
uint32_t surf = p_atomic_read(&pool->surfs[scratch_size_log2]);
if (surf > 0)
return surf;
struct anv_bo *bo =
anv_scratch_pool_alloc(device, pool, MESA_SHADER_COMPUTE,
per_thread_scratch);
struct anv_address addr = { .bo = bo };
struct anv_state state =
anv_state_pool_alloc(&device->surface_state_pool,
device->isl_dev.ss.size, 64);
isl_buffer_fill_state(&device->isl_dev, state.map,
.address = anv_address_physical(addr),
.size_B = bo->size,
.mocs = anv_mocs(device, bo, 0),
.format = ISL_FORMAT_RAW,
.swizzle = ISL_SWIZZLE_IDENTITY,
.stride_B = per_thread_scratch,
.is_scratch = true);
uint32_t current = p_atomic_cmpxchg(&pool->surfs[scratch_size_log2],
0, state.offset);
if (current) {
anv_state_pool_free(&device->surface_state_pool, state);
return current;
} else {
pool->surf_states[scratch_size_log2] = state;
return state.offset;
}
}
VkResult
anv_bo_cache_init(struct anv_bo_cache *cache, struct anv_device *device)
{

5
src/intel/vulkan_hasvk/anv_private.h
View file

@ -842,8 +842,6 @@ void anv_bo_pool_free(struct anv_bo_pool *pool, struct anv_bo *bo);
struct anv_scratch_pool {
/* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
struct anv_bo *bos[16][MESA_SHADER_STAGES];
uint32_t surfs[16];
struct anv_state surf_states[16];
};
void anv_scratch_pool_init(struct anv_device *device,
@ -854,9 +852,6 @@ struct anv_bo *anv_scratch_pool_alloc(struct anv_device *device,
struct anv_scratch_pool *pool,
gl_shader_stage stage,
unsigned per_thread_scratch);
uint32_t anv_scratch_pool_get_surf(struct anv_device *device,
struct anv_scratch_pool *pool,
unsigned per_thread_scratch);
/** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
struct anv_bo_cache {

19
src/intel/vulkan_hasvk/genX_pipeline.c
View file

@ -1319,25 +1319,6 @@ get_scratch_space(const struct anv_shader_bin *bin)
return ffs(bin->prog_data->total_scratch / 2048);
}
static UNUSED uint32_t
get_scratch_surf(struct anv_pipeline *pipeline,
gl_shader_stage stage,
const struct anv_shader_bin *bin)
{
if (bin->prog_data->total_scratch == 0)
return 0;
struct anv_bo *bo =
anv_scratch_pool_alloc(pipeline->device,
&pipeline->device->scratch_pool,
stage, bin->prog_data->total_scratch);
anv_reloc_list_add_bo(pipeline->batch.relocs,
pipeline->batch.alloc, bo);
return anv_scratch_pool_get_surf(pipeline->device,
&pipeline->device->scratch_pool,
bin->prog_data->total_scratch) >> 4;
}
static void
emit_3dstate_vs(struct anv_graphics_pipeline *pipeline)
{