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vulkan: Handle VIEW_INDEX_FROM_DEVICE_INDEX_BIT in the runtime
Reviewed-by: Ivan Briano <ivan.briano@intel.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30876>
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2 changed files with 7 additions and 28 deletions
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@ -346,8 +346,6 @@ struct anv_pipeline_stage {
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bool uses_bt_for_push_descs;
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bool view_index_from_device_index;
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enum anv_dynamic_push_bits dynamic_push_values;
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union brw_any_prog_data prog_data;
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@ -716,8 +714,6 @@ anv_pipeline_hash_graphics(struct anv_graphics_base_pipeline *pipeline,
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_mesa_sha1_update(&ctx, stages[s].shader_sha1,
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sizeof(stages[s].shader_sha1));
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_mesa_sha1_update(&ctx, &stages[s].key, brw_prog_key_size(s));
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bool vi_from_di = stages[s].view_index_from_device_index;
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_mesa_sha1_update(&ctx, &vi_from_di, sizeof(vi_from_di));
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}
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}
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@ -1918,8 +1914,6 @@ anv_graphics_lib_retain_shaders(struct anv_graphics_base_pipeline *pipeline,
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sizeof(stages[s].shader_sha1));
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lib->retained_shaders[s].subgroup_size_type = stages[s].subgroup_size_type;
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lib->retained_shaders[s].view_index_from_device_index =
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stages[s].view_index_from_device_index;
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nir_shader *nir = stages[s].nir != NULL ? stages[s].nir : stages[s].imported.nir;
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assert(nir != NULL);
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@ -2097,9 +2091,6 @@ anv_pipeline_nir_preprocess(struct anv_pipeline *pipeline,
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struct anv_device *device = pipeline->device;
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const struct brw_compiler *compiler = device->physical->compiler;
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if (stage->view_index_from_device_index)
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NIR_PASS(_, stage->nir, nir_lower_view_index_to_device_index);
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const struct nir_lower_sysvals_to_varyings_options sysvals_to_varyings = {
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.point_coord = true,
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};
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@ -2202,9 +2193,6 @@ anv_graphics_pipeline_compile(struct anv_graphics_base_pipeline *pipeline,
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const struct intel_device_info *devinfo = device->info;
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const struct brw_compiler *compiler = device->physical->compiler;
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bool view_index_from_device_index =
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(pipeline->base.flags & VK_PIPELINE_CREATE_2_VIEW_INDEX_FROM_DEVICE_INDEX_BIT_KHR) != 0;
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/* Setup the shaders given in this VkGraphicsPipelineCreateInfo::pStages[].
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* Other shaders imported from libraries should have been added by
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* anv_graphics_pipeline_import_lib().
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@ -2224,7 +2212,6 @@ anv_graphics_pipeline_compile(struct anv_graphics_base_pipeline *pipeline,
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stages[stage].pipeline_pNext = info->pNext;
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stages[stage].info = &info->pStages[i];
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stages[stage].feedback_idx = shader_count++;
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stages[stage].view_index_from_device_index = view_index_from_device_index;
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anv_stage_write_shader_hash(&stages[stage], device);
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}
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@ -3050,8 +3037,6 @@ anv_graphics_pipeline_import_lib(struct anv_graphics_base_pipeline *pipeline,
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stages[s].source_hash = lib->base.source_hashes[s];
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stages[s].subgroup_size_type = lib->retained_shaders[s].subgroup_size_type;
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stages[s].view_index_from_device_index =
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lib->retained_shaders[s].view_index_from_device_index;
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stages[s].imported.nir = lib->retained_shaders[s].nir;
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stages[s].imported.bin = lib->base.shaders[s];
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}
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@ -182,6 +182,9 @@ vk_pipeline_shader_stage_to_nir(struct vk_device *device,
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if (nir == NULL)
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return vk_errorf(device, VK_ERROR_UNKNOWN, "spirv_to_nir failed");
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if (pipeline_flags & VK_PIPELINE_CREATE_2_VIEW_INDEX_FROM_DEVICE_INDEX_BIT_KHR)
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NIR_PASS(_, nir, nir_lower_view_index_to_device_index);
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*nir_out = nir;
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return VK_SUCCESS;
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@ -220,6 +223,10 @@ vk_pipeline_hash_shader_stage(VkPipelineCreateFlags2KHR pipeline_flags,
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_mesa_sha1_init(&ctx);
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/* We only care about one of the pipeline flags */
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pipeline_flags &= VK_PIPELINE_CREATE_2_VIEW_INDEX_FROM_DEVICE_INDEX_BIT_KHR;
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_mesa_sha1_update(&ctx, &pipeline_flags, sizeof(pipeline_flags));
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_mesa_sha1_update(&ctx, &info->flags, sizeof(info->flags));
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assert(util_bitcount(info->stage) == 1);
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@ -822,16 +829,6 @@ vk_pipeline_precompile_shader(struct vk_device *device,
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uint8_t stage_sha1[SHA1_DIGEST_LENGTH];
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vk_pipeline_hash_shader_stage(pipeline_flags, info, &rs, stage_sha1);
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/* This bit affects shader compilation but isn't taken into account in
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* vk_pipeline_hash_shader_stage(). Re-hash the SHA1 if it's set.
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*/
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if (pipeline_flags & VK_PIPELINE_CREATE_2_VIEW_INDEX_FROM_DEVICE_INDEX_BIT_KHR) {
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struct mesa_sha1 ctx;
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_mesa_sha1_init(&ctx);
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_mesa_sha1_update(&ctx, stage_sha1, sizeof(stage_sha1));
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_mesa_sha1_final(&ctx, stage_sha1);
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}
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if (cache != NULL) {
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struct vk_pipeline_cache_object *cache_obj =
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vk_pipeline_cache_lookup_object(cache, stage_sha1, sizeof(stage_sha1),
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@ -860,9 +857,6 @@ vk_pipeline_precompile_shader(struct vk_device *device,
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if (result != VK_SUCCESS)
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return result;
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if (pipeline_flags & VK_PIPELINE_CREATE_2_VIEW_INDEX_FROM_DEVICE_INDEX_BIT_KHR)
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NIR_PASS(_, nir, nir_lower_view_index_to_device_index);
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if (ops->preprocess_nir != NULL)
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ops->preprocess_nir(device->physical, nir);
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