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radv: initialize workgroup_size in radv_meta_init_shader

Browse source 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14087>
This commit is contained in:
Rhys Perry 2021-12-07 11:57:34 +00:00 • committed by Marge Bot
parent 85161fb8ac
commit 420170fabc
13 changed files with 3 additions and 36 deletions
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6
src/amd/vulkan/radv_acceleration_structure.c
View file

@ -919,8 +919,6 @@ build_leaf_shader(struct radv_device *dev)
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "accel_build_leaf_shader");
b.shader->info.workgroup_size[0] = 64;
b.shader->info.workgroup_size[1] = 1;
b.shader->info.workgroup_size[2] = 1;
nir_ssa_def *pconst0 =
nir_load_push_constant(&b, 4, 32, nir_imm_int(&b, 0), .base = 0, .range = 16);
@ -1264,8 +1262,6 @@ build_internal_shader(struct radv_device *dev)
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "accel_build_internal_shader");
b.shader->info.workgroup_size[0] = 64;
b.shader->info.workgroup_size[1] = 1;
b.shader->info.workgroup_size[2] = 1;
/*
* push constants:
@ -1375,8 +1371,6 @@ build_copy_shader(struct radv_device *dev)
{
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "accel_copy");
b.shader->info.workgroup_size[0] = 64;
b.shader->info.workgroup_size[1] = 1;
b.shader->info.workgroup_size[2] = 1;
nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);
nir_ssa_def *wg_id = nir_load_workgroup_id(&b, 32);

3
src/amd/vulkan/radv_meta.c
View file

@ -565,6 +565,9 @@ nir_builder PRINTFLIKE(2, 3) radv_meta_init_shader(gl_shader_stage stage, const
}
b.shader->info.internal = true;
b.shader->info.workgroup_size[0] = 1;
b.shader->info.workgroup_size[1] = 1;
b.shader->info.workgroup_size[2] = 1;
return b;
}

4
src/amd/vulkan/radv_meta_buffer.c
View file

@ -9,8 +9,6 @@ build_buffer_fill_shader(struct radv_device *dev)
{
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_buffer_fill");
b.shader->info.workgroup_size[0] = 64;
b.shader->info.workgroup_size[1] = 1;
b.shader->info.workgroup_size[2] = 1;
nir_ssa_def *global_id = get_global_ids(&b, 1);
@ -33,8 +31,6 @@ build_buffer_copy_shader(struct radv_device *dev)
{
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_buffer_copy");
b.shader->info.workgroup_size[0] = 64;
b.shader->info.workgroup_size[1] = 1;
b.shader->info.workgroup_size[2] = 1;
nir_ssa_def *global_id = get_global_ids(&b, 1);

7
src/amd/vulkan/radv_meta_bufimage.c
View file

@ -42,7 +42,6 @@ build_nir_itob_compute_shader(struct radv_device *dev, bool is_3d)
radv_meta_init_shader(MESA_SHADER_COMPUTE, is_3d ? "meta_itob_cs_3d" : "meta_itob_cs");
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
b.shader->info.workgroup_size[2] = 1;
nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, sampler_type, "s_tex");
input_img->data.descriptor_set = 0;
input_img->data.binding = 0;
@ -224,7 +223,6 @@ build_nir_btoi_compute_shader(struct radv_device *dev, bool is_3d)
radv_meta_init_shader(MESA_SHADER_COMPUTE, is_3d ? "meta_btoi_cs_3d" : "meta_btoi_cs");
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
b.shader->info.workgroup_size[2] = 1;
nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, buf_type, "s_tex");
input_img->data.descriptor_set = 0;
input_img->data.binding = 0;
@ -403,7 +401,6 @@ build_nir_btoi_r32g32b32_compute_shader(struct radv_device *dev)
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_btoi_r32g32b32_cs");
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
b.shader->info.workgroup_size[2] = 1;
nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, buf_type, "s_tex");
input_img->data.descriptor_set = 0;
input_img->data.binding = 0;
@ -557,7 +554,6 @@ build_nir_itoi_compute_shader(struct radv_device *dev, bool is_3d, int samples)
is_3d ? "meta_itoi_cs_3d-%d" : "meta_itoi_cs-%d", samples);
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
b.shader->info.workgroup_size[2] = 1;
nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, buf_type, "s_tex");
input_img->data.descriptor_set = 0;
input_img->data.binding = 0;
@ -756,7 +752,6 @@ build_nir_itoi_r32g32b32_compute_shader(struct radv_device *dev)
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_itoi_r32g32b32_cs");
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
b.shader->info.workgroup_size[2] = 1;
nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, type, "input_img");
input_img->data.descriptor_set = 0;
input_img->data.binding = 0;
@ -916,7 +911,6 @@ build_nir_cleari_compute_shader(struct radv_device *dev, bool is_3d, int samples
MESA_SHADER_COMPUTE, is_3d ? "meta_cleari_cs_3d-%d" : "meta_cleari_cs-%d", samples);
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
b.shader->info.workgroup_size[2] = 1;
nir_variable *output_img = nir_variable_create(b.shader, nir_var_image, img_type, "out_img");
output_img->data.descriptor_set = 0;
@ -1073,7 +1067,6 @@ build_nir_cleari_r32g32b32_compute_shader(struct radv_device *dev)
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_cleari_r32g32b32_cs");
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
b.shader->info.workgroup_size[2] = 1;
nir_variable *output_img = nir_variable_create(b.shader, nir_var_image, img_type, "out_img");
output_img->data.descriptor_set = 0;

3
src/amd/vulkan/radv_meta_clear.c
View file

@ -1060,8 +1060,6 @@ build_clear_htile_mask_shader()
{
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_clear_htile_mask");
b.shader->info.workgroup_size[0] = 64;
b.shader->info.workgroup_size[1] = 1;
b.shader->info.workgroup_size[2] = 1;
nir_ssa_def *global_id = get_global_ids(&b, 1);
@ -1165,7 +1163,6 @@ build_clear_dcc_comp_to_single_shader(bool is_msaa)
is_msaa ? "multisampled" : "singlesampled");
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
b.shader->info.workgroup_size[2] = 1;
nir_ssa_def *global_id = get_global_ids(&b, 3);

1
src/amd/vulkan/radv_meta_copy_vrs_htile.c
View file

@ -47,7 +47,6 @@ build_copy_vrs_htile_shader(struct radv_device *device, struct radeon_surf *surf
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_copy_vrs_htile");
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
b.shader->info.workgroup_size[2] = 1;
/* Get coordinates. */
nir_ssa_def *global_id = get_global_ids(&b, 2);

1
src/amd/vulkan/radv_meta_dcc_retile.c
View file

@ -36,7 +36,6 @@ build_dcc_retile_compute_shader(struct radv_device *dev, struct radeon_surf *sur
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
b.shader->info.workgroup_size[2] = 1;
nir_ssa_def *src_dcc_size = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 0), .range = 8);
nir_ssa_def *src_dcc_pitch = nir_channels(&b, src_dcc_size, 1);

1
src/amd/vulkan/radv_meta_decompress.c
View file

@ -43,7 +43,6 @@ build_expand_depth_stencil_compute_shader(struct radv_device *dev)
/* We need at least 8/8/1 to cover an entire HTILE block in a single workgroup. */
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
b.shader->info.workgroup_size[2] = 1;
nir_variable *input_img = nir_variable_create(b.shader, nir_var_image, img_type, "in_img");
input_img->data.descriptor_set = 0;
input_img->data.binding = 0;

1
src/amd/vulkan/radv_meta_fast_clear.c
View file

@ -44,7 +44,6 @@ build_dcc_decompress_compute_shader(struct radv_device *dev)
/* We need at least 16/16/1 to cover an entire DCC block in a single workgroup. */
b.shader->info.workgroup_size[0] = 16;
b.shader->info.workgroup_size[1] = 16;
b.shader->info.workgroup_size[2] = 1;
nir_variable *input_img = nir_variable_create(b.shader, nir_var_image, img_type, "in_img");
input_img->data.descriptor_set = 0;
input_img->data.binding = 0;

1
src/amd/vulkan/radv_meta_fmask_copy.c
View file

@ -33,7 +33,6 @@ build_fmask_copy_compute_shader(struct radv_device *dev, int samples)
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
b.shader->info.workgroup_size[2] = 1;
nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, sampler_type, "s_tex");
input_img->data.descriptor_set = 0;

1
src/amd/vulkan/radv_meta_fmask_expand.c
View file

@ -36,7 +36,6 @@ build_fmask_expand_compute_shader(struct radv_device *device, int samples)
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_fmask_expand_cs-%d", samples);
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
b.shader->info.workgroup_size[2] = 1;
nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, type, "s_tex");
input_img->data.descriptor_set = 0;

2
src/amd/vulkan/radv_meta_resolve_cs.c
View file

@ -68,7 +68,6 @@ build_resolve_compute_shader(struct radv_device *dev, bool is_integer, bool is_s
is_integer ? "int" : (is_srgb ? "srgb" : "float"));
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
b.shader->info.workgroup_size[2] = 1;
nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, sampler_type, "s_tex");
input_img->data.descriptor_set = 0;
@ -140,7 +139,6 @@ build_depth_stencil_resolve_compute_shader(struct radv_device *dev, int samples,
get_resolve_mode_str(resolve_mode), samples);
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
b.shader->info.workgroup_size[2] = 1;
nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, sampler_type, "s_tex");
input_img->data.descriptor_set = 0;

8
src/amd/vulkan/radv_query.c
View file

@ -119,8 +119,6 @@ build_occlusion_query_shader(struct radv_device *device)
*/
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "occlusion_query");
b.shader->info.workgroup_size[0] = 64;
b.shader->info.workgroup_size[1] = 1;
b.shader->info.workgroup_size[2] = 1;
nir_variable *result = nir_local_variable_create(b.impl, glsl_uint64_t_type(), "result");
nir_variable *outer_counter =
@ -257,8 +255,6 @@ build_pipeline_statistics_query_shader(struct radv_device *device)
*/
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "pipeline_statistics_query");
b.shader->info.workgroup_size[0] = 64;
b.shader->info.workgroup_size[1] = 1;
b.shader->info.workgroup_size[2] = 1;
nir_variable *output_offset =
nir_local_variable_create(b.impl, glsl_int_type(), "output_offset");
@ -397,8 +393,6 @@ build_tfb_query_shader(struct radv_device *device)
*/
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "tfb_query");
b.shader->info.workgroup_size[0] = 64;
b.shader->info.workgroup_size[1] = 1;
b.shader->info.workgroup_size[2] = 1;
/* Create and initialize local variables. */
nir_variable *result =
@ -522,8 +516,6 @@ build_timestamp_query_shader(struct radv_device *device)
*/
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "timestamp_query");
b.shader->info.workgroup_size[0] = 64;
b.shader->info.workgroup_size[1] = 1;
b.shader->info.workgroup_size[2] = 1;
/* Create and initialize local variables. */
nir_variable *result = nir_local_variable_create(b.impl, glsl_uint64_t_type(), "result");