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i965: Avoid double-negation of immediate values in the VS.

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In general, we have to negate in immediate values we pass in because
the src1 negate field in the register description is in the bits3 slot
that the 32-bit value is loaded into, so it's ignored by the hardware.
However, the src0 negate field is in bits1, so after we'd negated the
immediate value loaded in, it would also get negated through the
register description.  This broke this VP instruction in the position
calculation in civ4:

MAD TEMP[1], TEMP[1], CONST[256].zzzz, CONST[256].-y-y-y-y;

Bug #30156
(cherry picked from commit 1d1ad6306d)
This commit is contained in:
Eric Anholt 2011-01-07 14:26:39 -08:00 • committed by Ian Romanick
parent bf3932aad6
commit 41d4af17a1
1 changed files with 3 additions and 4 deletions
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7
src/mesa/drivers/dri/i965/brw_vs_emit.c
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@ -1224,11 +1224,10 @@ static struct brw_reg get_arg( struct brw_vs_compile *c,
GET_SWZ(src->Swizzle, 1),
GET_SWZ(src->Swizzle, 2),
GET_SWZ(src->Swizzle, 3));
}
/* Note this is ok for non-swizzle instructions:
*/
reg.negate = src->Negate ? 1 : 0;
/* Note this is ok for non-swizzle ARB_vp instructions */
reg.negate = src->Negate ? 1 : 0;
}
return reg;
}