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r300/compiler: add emulation of all mirrored-clamp wrap modes for NPOT textures

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This commit is contained in:
Marek Olšák 2010-04-17 02:43:47 +02:00
parent f91a06eed2
commit 411d506332
3 changed files with 24 additions and 3 deletions
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6
src/gallium/drivers/r300/r300_fs.c
View file

@ -169,10 +169,14 @@ static void get_external_state(
break;
case PIPE_TEX_WRAP_MIRROR_REPEAT:
state->unit[i].wrap_mode = RC_WRAP_MIRRORED_REPEAT;
state->unit[i].fake_npot = TRUE;
break;
case PIPE_TEX_WRAP_MIRROR_CLAMP:
case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
state->unit[i].wrap_mode = RC_WRAP_MIRROR;
state->unit[i].wrap_mode = RC_WRAP_MIRRORED_CLAMP;
state->unit[i].fake_npot = TRUE;
break;

3
src/mesa/drivers/dri/r300/compiler/radeon_code.h
View file

@ -115,7 +115,8 @@ typedef enum {
typedef enum {
RC_WRAP_NONE = 0,
RC_WRAP_REPEAT,
RC_WRAP_MIRROR
RC_WRAP_MIRRORED_REPEAT,
RC_WRAP_MIRRORED_CLAMP
} rc_wrap_mode;
/**

18
src/mesa/drivers/dri/r300/compiler/radeon_program_tex.c
View file

@ -233,7 +233,7 @@ int radeonTransformTEX(
inst_frc->U.I.DstReg.Index = temp;
inst_frc->U.I.DstReg.WriteMask = RC_MASK_XYZ;
inst_frc->U.I.SrcReg[0] = inst->U.I.SrcReg[0];
} else if (wrapmode == RC_WRAP_MIRROR) {
} else if (wrapmode == RC_WRAP_MIRRORED_REPEAT) {
/*
* Function:
* f(v) = 1 - abs(frac(v * 0.5) * 2 - 1)
@ -295,6 +295,22 @@ int radeonTransformTEX(
inst_add->U.I.SrcReg[1].Swizzle = RC_SWIZZLE_XYZ0;
inst_add->U.I.SrcReg[1].Abs = 1;
inst_add->U.I.SrcReg[1].Negate = RC_MASK_XYZ;
} else if (wrapmode == RC_WRAP_MIRRORED_CLAMP) {
/*
* Mirrored clamp modes are bloody simple, we just use abs
* to mirror [0, 1] into [-1, 0]. This works for
* all modes i.e. CLAMP, CLAMP_TO_EDGE, and CLAMP_TO_BORDER.
*/
struct rc_instruction *inst_mov;
inst_mov = rc_insert_new_instruction(c, inst->Prev);
inst_mov->U.I.Opcode = RC_OPCODE_MOV;
inst_mov->U.I.DstReg.File = RC_FILE_TEMPORARY;
inst_mov->U.I.DstReg.Index = temp;
inst_mov->U.I.DstReg.WriteMask = RC_MASK_XYZ;
inst_mov->U.I.SrcReg[0] = inst->U.I.SrcReg[0];
inst_mov->U.I.SrcReg[0].Abs = 1;
}
/* Preserve W for TXP/TXB. */