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nil: Rework the descriptor interface

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This adds a new Descriptor (nil_descriptor) struct and reworks all the
methods/functions to return a Descriptor.  This is less janky than all
the output pointers.  It also gives us a struct type that's the right
size so we're not declaring uint32_t[8] arrays everywhere.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35475>
This commit is contained in:
Faith Ekstrand 2025-06-11 15:18:52 -04:00 • committed by Marge Bot
parent 12e94a91e3
commit 40b59a5c26
7 changed files with 140 additions and 105 deletions
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1
src/nouveau/nil/cbindgen.toml
View file

@ -22,6 +22,7 @@ renaming_overrides_prefixing = true
"MAX_DRM_FORMAT_MODS" = "NIL_MAX_DRM_FORMAT_MODS"
# This is annoying. rename_types doesn't seem to work
"Descriptor" = "nil_descriptor"
"Format" = "nil_format"
"GOBType" = "nil_gob_type"
"Image" = "nil_image"

192
src/nouveau/nil/tic.rs → src/nouveau/nil/descriptor.rs
View file

@ -254,7 +254,7 @@ fn normalize_extent(image: &Image, view: &View) -> Extent4D<units::Pixels> {
extent
}
fn nv9097_fill_tic(
fn nv9097_fill_image_view_desc(
image: &Image,
view: &View,
base_address: u64,
@ -363,7 +363,7 @@ fn nv9097_fill_tic(
th.set_ufixed(cl9097::TEXHEADV2_MIN_LOD_CLAMP, min_lod_clamp);
}
fn nvb097_fill_tic(
fn nvb097_fill_image_view_desc(
dev: &nil_rs_bindings::nv_device_info,
image: &Image,
view: &View,
@ -529,7 +529,7 @@ pub const IDENTITY_SWIZZLE: [nil_rs_bindings::pipe_swizzle; 4] = [
nil_rs_bindings::PIPE_SWIZZLE_W,
];
fn nv9097_nil_fill_buffer_tic(
fn nv9097_nil_fill_buffer_desc(
base_address: u64,
format: Format,
num_elements: u32,
@ -552,7 +552,7 @@ fn nv9097_nil_fill_buffer_tic(
set_enum!(th, cl9097, TEXHEADV2_TEXTURE_TYPE, ONE_D_BUFFER);
}
fn nvb097_nil_fill_buffer_tic(
fn nvb097_nil_fill_buffer_desc(
base_address: u64,
format: Format,
num_elements: u32,
@ -584,62 +584,6 @@ fn nvb097_nil_fill_buffer_tic(
set_enum!(th, clb097, TEXHEAD_1D_SECTOR_PROMOTION, PROMOTE_TO_2_V);
}
impl Image {
#[no_mangle]
pub extern "C" fn nil_image_fill_tic(
&self,
dev: &nil_rs_bindings::nv_device_info,
view: &View,
base_address: u64,
desc_out: &mut [u32; 8],
) {
self.fill_tic(dev, view, base_address, desc_out);
}
pub fn fill_tic(
&self,
dev: &nil_rs_bindings::nv_device_info,
view: &View,
base_address: u64,
desc_out: &mut [u32; 8],
) {
if dev.cls_eng3d >= MAXWELL_A {
nvb097_fill_tic(dev, self, view, base_address, desc_out);
} else if dev.cls_eng3d >= FERMI_A {
nv9097_fill_tic(self, view, base_address, desc_out);
} else {
panic!("Tesla and older not supported");
}
}
}
#[no_mangle]
pub extern "C" fn nil_buffer_fill_tic(
dev: &nil_rs_bindings::nv_device_info,
base_address: u64,
format: Format,
num_elements: u32,
desc_out: &mut [u32; 8],
) {
fill_buffer_tic(dev, base_address, format, num_elements, desc_out);
}
pub fn fill_buffer_tic(
dev: &nil_rs_bindings::nv_device_info,
base_address: u64,
format: Format,
num_elements: u32,
desc_out: &mut [u32; 8],
) {
if dev.cls_eng3d >= MAXWELL_A {
nvb097_nil_fill_buffer_tic(base_address, format, num_elements, desc_out)
} else if dev.cls_eng3d >= FERMI_A {
nv9097_nil_fill_buffer_tic(base_address, format, num_elements, desc_out)
} else {
panic!("Tesla and older not supported");
}
}
pub const ZERO_SWIZZLE: [nil_rs_bindings::pipe_swizzle; 4] = [
nil_rs_bindings::PIPE_SWIZZLE_0,
nil_rs_bindings::PIPE_SWIZZLE_0,
@ -647,7 +591,7 @@ pub const ZERO_SWIZZLE: [nil_rs_bindings::pipe_swizzle; 4] = [
nil_rs_bindings::PIPE_SWIZZLE_0,
];
fn nv9097_fill_null_tic(zero_page_address: u64, desc_out: &mut [u32; 8]) {
fn nv9097_fill_null_desc(zero_page_address: u64, desc_out: &mut [u32; 8]) {
*desc_out = [0u32; 8];
let mut th = BitMutView::new(desc_out);
@ -669,7 +613,7 @@ fn nv9097_fill_null_tic(zero_page_address: u64, desc_out: &mut [u32; 8]) {
th.set_field(cl9097::TEXHEADV2_RES_VIEW_MAX_MIP_LEVEL, 0_u8);
}
fn nvb097_fill_null_tic(zero_page_address: u64, desc_out: &mut [u32; 8]) {
fn nvb097_fill_null_desc(zero_page_address: u64, desc_out: &mut [u32; 8]) {
*desc_out = [0u32; 8];
let mut th = BitMutView::new(desc_out);
@ -703,28 +647,116 @@ fn nvb097_fill_null_tic(zero_page_address: u64, desc_out: &mut [u32; 8]) {
th.set_field(clb097::TEXHEAD_BL_RESERVED7Y, 0x80_u8);
}
pub fn fill_null_tic(
dev: &nil_rs_bindings::nv_device_info,
zero_page_address: u64,
desc_out: &mut [u32; 8],
) {
if dev.cls_eng3d >= VOLTA_A {
// On Volta+, we can just fill with zeros
*desc_out = [0; 8]
} else if dev.cls_eng3d >= MAXWELL_A {
nvb097_fill_null_tic(zero_page_address, desc_out)
} else if dev.cls_eng3d >= FERMI_A {
nv9097_fill_null_tic(zero_page_address, desc_out)
} else {
panic!("Tesla and older not supported");
#[derive(Clone, Debug, Copy, PartialEq)]
#[repr(C)]
pub struct Descriptor {
pub bits: [u32; 8],
}
impl Descriptor {
pub fn image_view(
dev: &nil_rs_bindings::nv_device_info,
image: &Image,
view: &View,
base_address: u64,
) -> Self {
let mut desc = Descriptor { bits: [0_u32; 8] };
if dev.cls_eng3d >= MAXWELL_A {
nvb097_fill_image_view_desc(
dev,
image,
view,
base_address,
&mut desc.bits,
);
} else if dev.cls_eng3d >= FERMI_A {
nv9097_fill_image_view_desc(
image,
view,
base_address,
&mut desc.bits,
);
} else {
panic!("Tesla and older not supported");
}
desc
}
pub fn buffer(
dev: &nil_rs_bindings::nv_device_info,
base_address: u64,
format: Format,
num_elements: u32,
) -> Self {
let mut desc = Descriptor { bits: [0_u32; 8] };
if dev.cls_eng3d >= MAXWELL_A {
nvb097_nil_fill_buffer_desc(
base_address,
format,
num_elements,
&mut desc.bits,
)
} else if dev.cls_eng3d >= FERMI_A {
nv9097_nil_fill_buffer_desc(
base_address,
format,
num_elements,
&mut desc.bits,
)
} else {
panic!("Tesla and older not supported");
}
desc
}
pub fn null(
dev: &nil_rs_bindings::nv_device_info,
zero_page_address: u64,
) -> Self {
let mut desc = Descriptor { bits: [0_u32; 8] };
if dev.cls_eng3d >= VOLTA_A {
// On Volta+, we can just use zeros
} else if dev.cls_eng3d >= MAXWELL_A {
nvb097_fill_null_desc(zero_page_address, &mut desc.bits)
} else if dev.cls_eng3d >= FERMI_A {
nv9097_fill_null_desc(zero_page_address, &mut desc.bits)
} else {
panic!("Tesla and older not supported");
}
desc
}
}
#[no_mangle]
pub extern "C" fn nil_fill_null_tic(
pub extern "C" fn nil_image_view_descriptor(
dev: &nil_rs_bindings::nv_device_info,
image: &Image,
view: &View,
base_address: u64,
) -> Descriptor {
Descriptor::image_view(dev, image, view, base_address)
}
#[no_mangle]
pub extern "C" fn nil_buffer_descriptor(
dev: &nil_rs_bindings::nv_device_info,
base_address: u64,
format: Format,
num_elements: u32,
) -> Descriptor {
Descriptor::buffer(dev, base_address, format, num_elements)
}
#[no_mangle]
pub extern "C" fn nil_null_descriptor(
dev: &nil_rs_bindings::nv_device_info,
zero_page_address: u64,
desc_out: &mut [u32; 8],
) {
fill_null_tic(dev, zero_page_address, desc_out);
) -> Descriptor {
Descriptor::null(dev, zero_page_address)
}

2
src/nouveau/nil/lib.rs
View file

@ -5,12 +5,12 @@ extern crate nil_rs_bindings;
extern crate nvidia_headers;
mod copy;
mod descriptor;
mod extent;
mod format;
mod image;
mod modifiers;
mod su_info;
mod tic;
mod tiling;
pub trait ILog2Ceil {

10
src/nouveau/vulkan/nvk_buffer_view.c
View file

@ -69,14 +69,14 @@ nvk_CreateBufferView(VkDevice _device,
} else {
if (pdev->info.cls_eng3d >= MAXWELL_A ||
(buffer->vk.usage & VK_BUFFER_USAGE_2_UNIFORM_TEXEL_BUFFER_BIT_KHR)) {
uint32_t desc[8];
nil_buffer_fill_tic(&pdev->info, addr, nil_format(format),
view->vk.elements, &desc);
const struct nil_descriptor desc =
nil_buffer_descriptor(&pdev->info, addr, nil_format(format),
view->vk.elements);
uint32_t desc_index;
result = nvk_descriptor_table_add(dev, &dev->images,
desc, sizeof(desc),
&desc_index);
&desc, sizeof(desc),
&desc_index);
if (result != VK_SUCCESS) {
vk_buffer_view_destroy(&dev->vk, pAllocator, &view->vk);
return result;

8
src/nouveau/vulkan/nvk_device.c
View file

@ -179,18 +179,18 @@ nvk_CreateDevice(VkPhysicalDevice physicalDevice,
nvkmd_mem_unmap(dev->zero_page, 0);
result = nvk_descriptor_table_init(dev, &dev->images,
8 * 4 /* tic entry size */,
sizeof(struct nil_descriptor),
1024, 1024 * 1024);
if (result != VK_SUCCESS)
goto fail_zero_page;
/* Reserve the descriptor at offset 0 to be the null descriptor */
uint32_t null_tic[8] = { 0, };
nil_fill_null_tic(&pdev->info, dev->zero_page->va->addr, &null_tic);
const struct nil_descriptor null_desc =
nil_null_descriptor(&pdev->info, dev->zero_page->va->addr);
ASSERTED uint32_t null_image_index;
result = nvk_descriptor_table_add(dev, &dev->images,
null_tic, sizeof(null_tic),
&null_desc, sizeof(null_desc),
&null_image_index);
assert(result == VK_SUCCESS);
assert(null_image_index == 0);

8
src/nouveau/vulkan/nvk_edb_bview_cache.c
View file

@ -89,13 +89,13 @@ nvk_edb_bview_cache_add_bview(struct nvk_device *dev,
size_el = size_B / el_size_B;
}
uint32_t desc[8];
nil_buffer_fill_tic(&nvk_device_physical(dev)->info, base_addr,
nil_format(key.format), size_el, &desc);
const struct nil_descriptor desc =
nil_buffer_descriptor(&nvk_device_physical(dev)->info, base_addr,
nil_format(key.format), size_el);
uint32_t index;
VkResult result = nvk_descriptor_table_add(dev, &dev->images,
desc, sizeof(desc), &index);
&desc, sizeof(desc), &index);
if (result != VK_SUCCESS)
return result;

24
src/nouveau/vulkan/nvk_image_view.c
View file

@ -186,9 +186,9 @@ nvk_image_view_init(struct nvk_device *dev,
if (view->vk.usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
uint32_t tic[8];
nil_image_fill_tic(&nil_image, &pdev->info,
&nil_view, base_addr, &tic);
const struct nil_descriptor desc =
nil_image_view_descriptor(&pdev->info, &nil_image,
&nil_view, base_addr);
uint32_t desc_index = 0;
if (cap_info != NULL) {
@ -196,10 +196,12 @@ nvk_image_view_init(struct nvk_device *dev,
? cap.single_plane.sampled_desc_index
: cap.ycbcr.planes[view_plane].desc_index;
result = nvk_descriptor_table_insert(dev, &dev->images,
desc_index, tic, sizeof(tic));
desc_index,
&desc, sizeof(desc));
} else {
result = nvk_descriptor_table_add(dev, &dev->images,
tic, sizeof(tic), &desc_index);
&desc, sizeof(desc),
&desc_index);
}
if (result != VK_SUCCESS) {
nvk_image_view_finish(dev, view);
@ -236,20 +238,20 @@ nvk_image_view_init(struct nvk_device *dev,
if (image->vk.samples != VK_SAMPLE_COUNT_1_BIT)
nil_image = nil_msaa_image_as_sa(&nil_image);
uint32_t tic[8];
nil_image_fill_tic(&nil_image, &pdev->info, &nil_view,
base_addr, &tic);
const struct nil_descriptor desc =
nil_image_view_descriptor(&pdev->info, &nil_image,
&nil_view, base_addr);
uint32_t desc_index = 0;
if (cap_info != NULL) {
assert(view->plane_count == 1);
desc_index = cap.single_plane.storage_desc_index;
result = nvk_descriptor_table_insert(dev, &dev->images,
desc_index, tic,
sizeof(tic));
desc_index, &desc,
sizeof(desc));
} else {
result = nvk_descriptor_table_add(dev, &dev->images,
tic, sizeof(tic),
&desc, sizeof(desc),
&desc_index);
}
if (result != VK_SUCCESS) {